公开(公告)号：US20080044724A1

公开(公告)日：2008-02-21

申请号：US11729975

申请日：2007-03-30

申请人： Hiroyuki Inoue ,  Masahiro Hosoda ,  Takaaki Aoto

发明人： Hiroyuki Inoue ,  Masahiro Hosoda ,  Takaaki Aoto

IPC分类号： H01M2/02 ,  H01M10/02 ,  H01M2/14

CPC分类号： H01M2/0413 ,  H01M2/046 ,  H01M2/1223 ,  H01M2/1276 ,  H01M10/30

摘要： The aim is to provide a sealed secondary battery with an electrode body that is larger in volume and thus incapacity, without affecting the operability of a valve member and the battery hermeticity. To achieve the aim, the sealed secondary battery includes an electrode body, an external casing, a closure plate, and a valve member. The external casing is of a tubular shape having a bottom and an opening. The closure plate has a hole formed through a central portion thereof and is secured at a peripheral portion to the edge of the opening of the external casing. The valve member has a resilient portion and a plate portion. The plate portion is biased by the resilient portion against the closure plate to close off the hole. The closure plate is smaller in average thickness at portions opposite a main surface of the plate portion than at other portions.

摘要翻译： 其目的是提供具有体积较大并因此丧失能力的电极体的密封二次电池，而不影响阀构件的可操作性和电池气密性。 为了达到目的，密封二次电池包括电极体，外壳，封闭板和阀构件。 外壳是具有底部和开口的管状。 封闭板具有通过其中心部分形成的孔，并且被固定在外壳的开口的边缘的周边部分处。 阀构件具有弹性部分和板部分。 板部分由弹性部分抵靠封闭板偏压以关闭孔。 闭合板在与板部分的主表面相对的部分处的平均厚度小于在其它部分处的平均厚度。

公开(公告)号：US07226693B2

公开(公告)日：2007-06-05

申请号：US10022284

申请日：2001-12-20

申请人： Kei Tomihara ,  Masahiro Hosoda

发明人： Kei Tomihara ,  Masahiro Hosoda

IPC分类号： H01M2/16 ,  H01M6/04 ,  H01M4/02 ,  H01M4/60

CPC分类号： H01M4/667 ,  H01M4/0416 ,  H01M4/246 ,  H01M4/366 ,  H01M10/30 ,  Y02E60/124 ,  Y02P70/54 ,  Y10T29/49115

摘要： A method for producing a cadmium negative electrode for alkaline batteries according to the present invention comprises a step of obtaining a cadmium active-substance impregnated electrode plate by impregnating said electrode substrate with a cadmium active substance; and a step of adding polyethylene glycol for forming a polyethylene glycol coating on the surface of said cadmium negative electrode or on the surface of said active substance by coating or impregnating said active-substance impregnated electrode with polyethylene glycol.

摘要翻译： 本发明的碱性电池用镉负极的制造方法包括通过用镉活性物质浸渍所述电极基板来获得镉活性物质浸渍电极板的工序; 以及通过用聚乙二醇涂布或浸渍所述活性物质浸渍电极，在所述镉负极的表面上或所述活性物质的表面上添加用于形成聚乙二醇涂层的聚乙二醇的步骤。

公开(公告)号：US06186667B1

公开(公告)日：2001-02-13

申请号：US09225356

申请日：1999-01-05

申请人： Yuji Nakamura ,  Hiroya Miyazaki ,  Masahiro Hosoda ,  Hideo Ouchi

发明人： Yuji Nakamura ,  Hiroya Miyazaki ,  Masahiro Hosoda ,  Hideo Ouchi

IPC分类号： F16C1908

CPC分类号： G01P3/443 ,  F16C19/185 ,  F16C33/7853 ,  F16C33/7876 ,  F16C33/805 ,  F16C41/007 ,  F16C2326/02

摘要： A rolling bearing unit comprising a rotatable race having an inner peripheral surface formed with an outer ring raceway and an outer peripheral surface formed with a rotating flange, a stationary race having an outer peripheral surface formed with an inner ring raceway, a plurality of rolling members between the outer ring raceway and the inner ring raceway, an annular encoder of multi-pole magnet supported in a concentric relation with the rotatable race to have characteristics alternately changed with a uniform interval in the circumferential direction and having an outer diameter larger than the outer diameter of the rotatable race, and a metal ring for supporting the encoder onto the rotatable race and having a cylindrical portion provided to enclose the encoder.

摘要翻译： 一种滚动轴承单元，包括具有形成有外圈滚道的内周面和形成有旋转凸缘的外周面的可旋转座圈，具有形成有内圈滚道的外周面的固定座圈，多个滚动构件 在外圈滚道和内圈滚道之间，具有与可旋转座圈同心关系的多极磁体的环形编码器，其特征在周向上以均匀的间隔交替变化，并且外径大于外圈 可旋转的座圈的直径，以及用于将编码器支撑在可旋转座圈上并具有设置成包围编码器的圆柱形部分的金属环。

公开(公告)号：US5360762A

公开(公告)日：1994-11-01

申请号：US080004

申请日：1993-06-21

申请人： Kosei Takahashi ,  Masahiro Hosoda ,  Atsuo Tsunoda ,  Takahiro Suyama ,  Sadayoshi Matsui

发明人： Kosei Takahashi ,  Masahiro Hosoda ,  Atsuo Tsunoda ,  Takahiro Suyama ,  Sadayoshi Matsui

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L31/105 ,  H01L31/18 ,  H01L33/00 ,  H01S5/042 ,  H01S5/20 ,  H01S5/223 ,  H01S5/32 ,  H01S5/323

CPC分类号： H01S5/32325 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/02658 ,  H01L31/105 ,  H01L31/1844 ,  H01L33/0062 ,  H01S5/2231 ,  H01S2304/02 ,  H01S5/0421 ,  H01S5/209 ,  H01S5/3211 ,  Y02E10/544 ,  Y02P70/521 ,  Y10S148/095

摘要： On a GaAs substrate (Al.sub.Y Ga.sub.1-Y).sub.0.5 In.sub.0.5 P crystal layers (0.ltoreq.Y.ltoreq.1) is formed to be lattice-matched with the substrate. By radiating As molecular beams on the surface of the crystal layers while heating the layered substrate to a temperature at which In in the crystal layers evaporates, the portion near the surface of the crystal layers is changed into an Al.sub.Y Ga.sub.1-Y As crystal layer (0.ltoreq.Y.ltoreq.1) of a thickness of several molecules, on which layer an Al.sub.X Ga.sub.1-X As crystal layer (0.ltoreq.X.ltoreq.1) is formed. Since the surface of the Al.sub.Y Ga.sub.1-Y As crystal layer has been purl fled, the formed Al.sub.X Ga.sub.1-X As crystal layer has a high crystallinity, allowing production of a light emitting diode, a semiconductor laser device and the like with high efficiency.

摘要翻译： 在GaAs衬底（AlYGa1-Y）上，形成与衬底晶格匹配的0.5In0.5P晶体层（0≤Y≤1）。 通过在层叠基板的加热的同时将As分子束照射到晶体层中的In蒸发的温度，将结晶层的表面附近的部分变更为AlYGa1-YAs晶体层（0 < / = Y <1），其上形成有AlXGa1-XAs晶体层（0≤X≤1）的几个分子的厚度。 由于AlYGa1-YAs晶体层的表面已经被剥离，所形成的AlXGa1-XAs晶体层具有高结晶度，从而能够以高效率制造发光二极管，半导体激光器件等。

公开(公告)号：US20100301902A1

公开(公告)日：2010-12-02

申请号：US12845290

申请日：2010-07-28

申请人： Mitsuhiro TOMOEDA ,  Makoto Muneyasu ,  Masahiro Hosoda

发明人： Mitsuhiro TOMOEDA ,  Makoto Muneyasu ,  Masahiro Hosoda

IPC分类号： G11C8/00

CPC分类号： H03K19/20 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08

摘要： A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

摘要翻译： 获得正常可操作的解码器电路，而不需要解码操作的延迟，电路面积的增加和电路设计成本的增加。 高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间，并在其栅电极处接收输入信号。 高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。 一个PMOS晶体管在其栅电极处接收控制信号。 另一个PMOS晶体管在其栅电极处接收控制信号。 逆变器接收从节点获得的信号作为输入信号，并将其反相信号作为输出信号输出。

公开(公告)号：US07795922B2

公开(公告)日：2010-09-14

申请号：US12361755

申请日：2009-01-29

申请人： Mitsuhiro Tomoeda ,  Makoto Muneyasu ,  Masahiro Hosoda

发明人： Mitsuhiro Tomoeda ,  Makoto Muneyasu ,  Masahiro Hosoda

IPC分类号： G11C8/00 ,  H03K19/082 ,  H03K19/094

CPC分类号： H03K19/20 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08

摘要： A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

摘要翻译： 获得正常可操作的解码器电路，而不需要解码操作的延迟，电路面积的增加和电路设计成本的增加。 高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间，并在其栅电极处接收输入信号。 高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。 一个PMOS晶体管在其栅电极处接收控制信号。 另一个PMOS晶体管在其栅电极处接收控制信号。 逆变器接收从节点获得的信号作为输入信号，并将其反相信号作为输出信号输出。

公开(公告)号：US06682076B1

公开(公告)日：2004-01-27

申请号：US09541697

申请日：2000-04-03

申请人： Masahiro Hosoda ,  Yuji Nakamura

发明人： Masahiro Hosoda ,  Yuji Nakamura

IPC分类号： F16J1534

CPC分类号： F16C33/7883 ,  F16C19/186 ,  F16C41/007 ,  F16C2326/02 ,  G01P3/443

摘要： A combination seal ring with an encoder for use to close off the opening of the space between a fixed ring and a rotational ring and to detect a rotational speed of the rotational ring, comprising a seal ring secured to the fixed ring, a metal slinger secured to the rotational ring, and an encoder of a rubber magnet secured to the slinger, the seal ring comprising a metal core secured to the fixed ring, and a fixed ring portion bent toward the rotational ring from the fixed cylindrical portion; and a resilient member bonded all around the metal core, the slinger comprising a rotational cylindrical portion secured to the rotational ring, and a rotational ring portion bent toward the fixed ring from the rotational cylindrical portion, the encoder bonded on the rotational circular ring portion, opposite to the seal lips by a molding process, the end rim of the encoder being short at least 0.2 mm of the end rim of the rotational circular ring portion.

摘要翻译： 一种具有编码器的组合密封环，用于封闭固定环和旋转环之间的空间的开口并且检测旋转环的旋转速度，包括固定到固定环的密封环，固定的金属抛油环 以及固定到抛油环的橡胶磁体的编码器，所述密封环包括固定到所述固定环的金属芯，以及从所述固定圆筒部向所述旋转环弯曲的固定环部; 以及弹性构件，其整体结合在所述金属芯周围，所述抛油环包括固定到所述旋转环的旋转圆柱形部分和从所述旋转圆柱部分朝向所述固定环弯曲的旋转环部分，所述编码器接合在所述旋转圆环部分上， 通过模制工艺与密封唇相对，编码器的端缘短于旋转圆环部分的端缘的至少0.2mm。

公开(公告)号：US06424587B1

公开(公告)日：2002-07-23

申请号：US09774801

申请日：2001-02-01

申请人： Masahiro Hosoda

发明人： Masahiro Hosoda

IPC分类号： G11C800

CPC分类号： G11C29/48

摘要： A semiconductor memory device includes an inner circuit. The inner circuit includes a command user interface, a logical circuit and a pad. Based upon an externally input fixing command, the command user interface outputs signals A and B with H or L level. Upon receipt of the signal A of H level and the signal B of L level, the logical circuit outputs a fixed logical signal of H level independent of the signal received from the pad, and upon receipt of the signal A of L level and the signal B of H level, outputs a fixed logical signal of L level independent of the signal received from the pad. Thus, it becomes possible to carry out a high-quality testing operation even when the number of the test pins of a test device is smaller than the number of address pins or data pins of a semiconductor memory device.

摘要翻译： 半导体存储器件包括内部电路。 内部电路包括命令用户接口，逻辑电路和焊盘。 基于外部输入固定命令，命令用户界面以H或L电平输出信号A和B. 在接收到H电平的信号A和L电平的信号B时，逻辑电路输出与电平接收的信号无关的H电平的固定逻辑信号，并且在接收到L电平的信号A和信号 B的H电平，输出固定的L电平的逻辑信号，与从焊盘接收的信号无关。 因此，即使当测试装置的测试引脚的数量小于半导体存储器件的地址引脚或数据引脚的数量时，也可以进行高质量的测试操作。

公开(公告)号：US5886096A

公开(公告)日：1999-03-23

申请号：US916450

申请日：1997-08-22

申请人： Miho Yoshida ,  Tsunetoshi Matsuda ,  Masahiro Hosoda

发明人： Miho Yoshida ,  Tsunetoshi Matsuda ,  Masahiro Hosoda

IPC分类号： C08K3/22 ,  C08J3/09 ,  C08L77/00

CPC分类号： C08K3/22 ,  C08K2003/2217 ,  C08K2003/222

摘要： A polyamide resin composition comprising a polyamide and an alkaline earth metal compound, wherein the amount of a cyclic monomer formed by melting said composition under the conditions of a moisture content of 0.02% by weight or less, at 0.01 Torr or below, at 250.degree. C., and for 8 hours is not more than 0.7 parts by weight per 100 parts by weight of the polyamide; and fibers, films and molded articles with the use of the same.

摘要翻译： 包含聚酰胺和碱土金属化合物的聚酰胺树脂组合物，其中通过在0.01Torr或更低的水分含量为0.02重量％或更低的条件下在250℃下将所述组合物熔化而形成的环状单体的量 并且8小时不超过每100重量份聚酰胺0.7重量份; 以及使用其的纤维，膜和模制品。

公开(公告)号：US5027169A

公开(公告)日：1991-06-25

申请号：US531386

申请日：1990-06-01

申请人： Kosei Takahashi ,  Masahiro Hosoda ,  Atsuo Tsunoda ,  Masafumi Kondo ,  Takahiro Suyama

发明人： Kosei Takahashi ,  Masahiro Hosoda ,  Atsuo Tsunoda ,  Masafumi Kondo ,  Takahiro Suyama

IPC分类号： H01L21/203 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/20 ,  H01L29/04

CPC分类号： H01L33/16 ,  B82Y20/00 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02433 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L29/045 ,  H01L33/0062 ,  H01L33/06

摘要： A semiconductor device comprising a (111)B single-crystalline semiconductor substrate which is misoriented toward (110), and epitaxial layers grown on the substrate by molecular beam epitaxy, whereby the crystallinity and luminescence efficiency of epitaxial layers are significantly improved.