公开(公告)号：US20190006251A1

公开(公告)日：2019-01-03

申请号：US15638704

申请日：2017-06-30

申请人： Intel Corporation

发明人： Bassam Ziadeh ,  John Lofgren ,  Santosh Pabba ,  Kevin Pounds ,  Alin Ila

IPC分类号： H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H05K13/00

CPC分类号： H01L23/13 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2221/68309 ,  H01L2221/68313 ,  H05K13/0084

摘要： A carrier medium for a semiconductor die includes a carrier tape with at least one pocket for the die to sit in and a selectively applied non-activated adhesive on the carrier tape.

公开(公告)号：US10037976B2

公开(公告)日：2018-07-31

申请号：US15704720

申请日：2017-09-14

申请人： INTEL CORPORATION

发明人： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US09793244B2

公开(公告)日：2017-10-17

申请号：US14654814

申请日：2014-07-11

申请人： INTEL CORPORATION

发明人： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/00 ,  H01L25/065 ,  H01L25/03 ,  H01L25/10 ,  H01L23/29 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20160260690A1

公开(公告)日：2016-09-08

申请号：US14654814

申请日：2014-07-11

申请人： Intel Corporation

发明人： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/29

CPC分类号： H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了集成电路（IC）组件和相关技术和配置的可扩展封装体系结构。 在一个实施例中，集成电路（IC）组件包括具有第一侧和与第一侧相对设置的第二侧的封装衬底，第一管芯具有与封装衬底的第一侧耦合的有源侧和不活动侧 所述第一管芯具有配置成在所述第一管芯和第二管芯之间布置电信号的一个或多个穿硅通孔（TSV）以及设置在所述封装基板的第一侧上的模具化合物，其中， 模具化合物在活性侧和非活性侧之间与第一模具的侧壁直接接触，并且其中距离第一侧最远的模具化合物的第一侧和终止边缘之间的距离等于或小于 而不是第一模具的不活动侧和第一侧之间的距离。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10580758B2

公开(公告)日：2020-03-03

申请号：US16044018

申请日：2018-07-24

申请人： INTEL CORPORATION

发明人： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC分类号： H01L25/065 ,  H01L25/03 ,  H01L25/10 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US10483177B2

公开(公告)日：2019-11-19

申请号：US15638704

申请日：2017-06-30

申请人： Intel Corporation

发明人： Bassam Ziadeh ,  John Lofgren ,  Santosh Pabba ,  Kevin Pounds ,  Alin Ila

IPC分类号： H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H05K13/00

摘要： A carrier medium for a semiconductor die includes a carrier tape with at least one pocket for the die to sit in and a selectively applied non-activated adhesive on the carrier tape.

公开(公告)号：US20180331075A1

公开(公告)日：2018-11-15

申请号：US16044018

申请日：2018-07-24

申请人： INTEL CORPORATION

发明人： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L25/10 ,  H01L25/03

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

公开(公告)号：US20180005997A1

公开(公告)日：2018-01-04

申请号：US15704720

申请日：2017-09-14

申请人： INTEL CORPORATION

发明人： Sanka Ganesan ,  Bassam Ziadeh ,  Nitesh Nimkar

IPC分类号： H01L25/065 ,  H01L25/10 ,  H01L23/29 ,  H01L25/03 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/293 ,  H01L24/02 ,  H01L24/03 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0381 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/27 ,  H01L2224/28105 ,  H01L2224/29006 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/3301 ,  H01L2224/33106 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80903 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

摘要： Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.