公开(公告)号：US20020113324A1

公开(公告)日：2002-08-22

申请号：US10131803

申请日：2002-04-24

申请人： International Business Machines Corporation

发明人： Steven A. Cordes ,  Peter A. Gruber ,  James L. Speidell ,  Wayne J. Howell ,  Thomas G. Ference

IPC分类号： H01L021/44 ,  H01L023/48 ,  H01L029/40 ,  H01L023/52

CPC分类号： H01L21/4857 ,  H01L21/4867 ,  H01L2924/0002 ,  H05K3/101 ,  H05K3/107 ,  H05K3/3421 ,  H05K2201/0305 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2203/128 ,  H01L2924/00

摘要： A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

公开(公告)号：US20020111010A1

公开(公告)日：2002-08-15

申请号：US09781121

申请日：2001-02-09

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC分类号： H01L021/44

CPC分类号： H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

摘要翻译： 描述了用于形成适用于引线键合和焊料凸块倒装芯片连接（例如受控崩溃芯片连接（C4））的公共输入 - 输出（I / O）站点的过程。 本发明特别适用于使用铜作为互连材料的半导体芯片，其中用于制造这种芯片的软电介质容易受到结合力的损害。 本发明通过在衬垫的顶表面上提供具有贵金属的部位同时提供扩散阻挡层来保持金属互连的高导电性来降低损坏的风险。 通过提供一种在衬底中形成的特征中选择性地沉积金属层的方法来减少在衬底内形成I / O部位的工艺步骤。 由于本发明的I / O站点可以用于引线键合或焊料凸块连接，这为芯片互连选项提供了增加的灵活性，同时也降低了工艺成本。

公开(公告)号：US20020062556A1

公开(公告)日：2002-05-30

申请号：US10055294

申请日：2002-01-22

申请人： International Business Machines Corporation

发明人： Guy P. Brouillette ,  David H. Danovitch ,  Peter A. Gruber ,  Michael Liehr ,  Carlos J. Sambucetti

IPC分类号： H05K001/11 ,  H01R012/04 ,  H05K003/34

CPC分类号： H01L21/563 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  H01L2924/00

摘要： A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads. In the bonded assembly, the in-situ polymeric mold layer and the underfill material layer forms a composite underfill to replace a conventional underfill material that must be injected between bonded chip and substrate by a capillary action in a time consuming process.

公开(公告)号：US20040087046A1

公开(公告)日：2004-05-06

申请号：US10688418

申请日：2003-10-17

申请人： International Business Machines Corporation.

发明人： Madhav Datta ,  Peter A. Gruber ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  George F. Walker

IPC分类号： H01L021/66

CPC分类号： H01L24/13 ,  B23K1/0016 ,  B23K1/20 ,  B23K2101/36 ,  G01R31/2886 ,  H01L22/00 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1148 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H01L2924/00014

摘要： A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than null of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.

摘要翻译： 公开了一种在平坦焊料凸块上测试集成电路芯片的方法以及配备有平坦焊料凸块的IC芯片。 在该方法中，首先提供具有多个接合焊盘和多个平坦焊料凸块的IC芯片，其中每个焊料凸块在多个焊盘上具有小于其直径的1/2的高度。 因此，探针线可以容易地用于接触焊料凸块上的增加的目标区域，以建立与测试电路的电连接。 探针可以容易地进行，凸块的所有Z高度基本相等。 焊料凸块的高度可以通过平面化处理来适当地控制，其中软焊料凸块被平面表面压缩，或者通过用于形成焊料凸块的MSS或电镀工艺在原位模具中形成焊料凸块 呈短圆柱形。 当使用MSS方法种植凸块时，焊料凸块以大致平坦的半球形转移到晶片表面上。

公开(公告)号：US20020175438A1

公开(公告)日：2002-11-28

申请号：US10191378

申请日：2002-07-08

申请人： International Business Machines Corporation

发明人： Peter A. Gruber ,  Frederic Maurer ,  Lubomyr Taras Romankiw

IPC分类号： B29C045/14 ,  B29C045/63

CPC分类号： H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  H01L2924/00

摘要： An apparatus and a method for filling high aspect ratio holes in electronic substrates that can be advantageously used for filling holes having aspect ratios larger than 5:1 are disclosed. In the apparatus, a filler plate and a vacuum plate are used in conjunction with a connection means such that a gap is formed between the two plates to accommodate an electronic substrate equipped with high aspect ratio via holes. The filler plate is equipped with an injection slot while the vacuum plate is equipped with a vacuum slot such that when a substrate is sandwiched therein, via holes can be evacuated of air and injected with a liquid simultaneously from a bottom side and a top side of the substrate. The present invention novel apparatus and method allows the filling of via holes that have small diameters, i.e., as small as 10 nullm, and high aspect ratios, i.e., at least 5:1 to be filled with an electrically conductive material such as a solder or a conductive polymer such that vias or interconnects can be formed in electronic substrates. The present invention apparatus and method can be advantageously used in fabricating substrates for display panels by forming conductive vias and interconnects for placing a voltage potential on pixel display elements formed on the display panels.

摘要翻译： 公开了一种用于填充电子基板中的高纵横比孔的装置和方法，其可以有利地用于填充具有大于5:1的纵横比的孔。 在装置中，填充板和真空板与连接装置结合使用，使得在两个板之间形成间隙以容纳配备有高纵横比通孔的电子基板。 填充板配备有注入槽，而真空板配备有真空槽，使得当基板夹在其中时，通孔可以从空气排出并同时从液体的底侧和顶侧注入液体 底物。 本发明的新型装置和方法允许填充具有小直径，即小至10um，高纵横比，即至少5:1的通孔，以填充诸如焊料的导电材料 或导电聚合物，使得可以在电子基板中形成通孔或互连。 本发明的装置和方法可以有利地用于制造用于显示面板的基板，通过形成用于在形成在显示面板上的像素显示元件上放置电压电位的导电通孔和互连。

公开(公告)号：US20020023945A1

公开(公告)日：2002-02-28

申请号：US09862371

申请日：2001-05-22

申请人： International Business Machines Corporation

发明人： Peter A. Gruber ,  Lannie R. Bolde ,  Guy P. Brouillette ,  James H. Covell ,  David Danovitch ,  Chon C. Lei

IPC分类号： B23K031/02 ,  B23K035/24 ,  B23K035/14 ,  B05D001/32 ,  B05D005/12

CPC分类号： H05K3/3468 ,  B23K3/0638 ,  B23K35/0222 ,  B23K2101/40 ,  H01L21/4846 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/0415 ,  H05K2203/074 ,  H05K2203/128

摘要： A method for joining a multiplicity of multi-alloy solder columns to an electronic substrate and the structure formed by such method are disclosed. In the method, a mold plate equipped with a multiplicity of cavities is first filled by an injection molded solder technique with a high temperature solder forming a multiplicity of solder columns. The mold plate is then sandwiched between an extraction plate and a transfer plate by utilizing a multiplicity of displacement means equipped in the extraction plate to displace the multiplicity of solder columns from the mold plate into a multiplicity of apertures equipped in the transfer plate. The multiplicity of cavities in the transfer plate each has a straight opening and a flared opening. The flared opening is then filled with a low temperature solder paste to encapsulate one end of the high temperature solder column. The low temperature solder paste is then reflown on top of a conductive pad on an electronic substrate at a temperature lower than the melting temperature of the high temperature solder to form a bond between the solder column and the conductive pad.

摘要翻译： 公开了一种将多种多合金焊料柱连接到电子基板的方法以及通过这种方法形成的结构。 在该方法中，首先通过注射成型的焊接技术填充配备有多个空腔的模板，其中高温焊料形成多个焊料柱。 然后通过利用设置在提取板中的多个位移装置将模板夹在提取板和转印板之间，以将多个焊料柱从模板移位成装配在转印板中的多个孔。 传递板中的多个空腔各具有直的开口和扩口的开口。 然后用扩散的开口填充低温焊膏以封装高温焊料柱的一端。 然后在低于高温焊料的熔融温度的温度下，将低温焊膏在电子基板上的导电焊盘的顶部上进行退火，以在焊料柱和导电焊盘之间形成接合。