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公开(公告)号：US10390439B2
公开(公告)日：2019-08-20
申请号：US15839464
申请日：2017-12-12
Applicant: International Business Machines Corporation
Inventor： Brian L. Carlson , John R. Dangler , Roger S. Krabbenhoft , Kevin A. Splittstoesser
IPC: H05K3/26 , H05K3/06 , H01P3/02 , H05K1/02 , H05K1/11 , H05K1/18 , H05K3/46 , H05K1/09 , H05K3/38 , H05K1/03
Abstract: A circuit apparatus includes at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.
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公开(公告)号：US10175064B2
公开(公告)日：2019-01-08
申请号：US14865610
申请日：2015-09-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： William L. Brodsky , Silvio Dragone , Roger S. Krabbenhoft , David C. Long , Stefano S. Oggioni , Michael T. Peets , William Santiago-Fernandez
Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.
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公开(公告)号：US20180103548A1
公开(公告)日：2018-04-12
申请号：US15839464
申请日：2017-12-12
Applicant: International Business Machines Corporation
Inventor： Brian L. Carlson , John R. Dangler , Roger S. Krabbenhoft , Kevin A. Splittstoesser
IPC: H05K3/26 , H05K1/11 , H05K1/18 , H05K3/46 , H01P3/02 , H05K3/38 , H05K1/02 , H05K3/06 , H05K1/09 , H05K1/03
CPC classification number: H05K3/26 , H01P3/02 , H05K1/0213 , H05K1/0237 , H05K1/0242 , H05K1/0298 , H05K1/0393 , H05K1/09 , H05K1/111 , H05K1/115 , H05K1/181 , H05K3/06 , H05K3/064 , H05K3/382 , H05K3/46 , H05K3/4611 , H05K2201/0355 , H05K2201/0391 , Y10T29/49117 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156
Abstract: A circuit apparatus includes at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.
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公开(公告)号：US20170079131A1
公开(公告)日：2017-03-16
申请号：US14855635
申请日：2015-09-16
Applicant: International Business Machines Corporation
Inventor： Brian L. Carlson , John R. Dangler , Roger S. Krabbenhoft , Kevin A. Splittstoesser
CPC classification number: H05K3/26 , H01P3/02 , H05K1/0213 , H05K1/0237 , H05K1/0242 , H05K1/0298 , H05K1/0393 , H05K1/09 , H05K1/111 , H05K1/115 , H05K1/181 , H05K3/06 , H05K3/064 , H05K3/382 , H05K3/46 , H05K3/4611 , H05K2201/0355 , H05K2201/0391 , Y10T29/49117 , Y10T29/49124 , Y10T29/49155 , Y10T29/49156
Abstract: A circuit apparatuses include at least one circuit feature formed from patterning a conductive sheet. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions of the circuit apparatus and is maintained in second regions of the circuit apparatus. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.
Abstract translation: 电路装置包括由图案化导电片形成的至少一个电路特征。 导电片包括不规则表面和平坦化表面。 电路装置的第一区域的导电片粗糙度最小化，并保持在电路装置的第二区域。 选择性地平坦化导电片的部分允许利用较低成本的较粗糙的导电片。 平坦化表面允许增加的信号完整性和降低的插入损耗，并且不规则表面允许增加电路装置的粘附性和增强可靠性。
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公开(公告)号：US20230397331A1
公开(公告)日：2023-12-07
申请号：US17805229
申请日：2022-06-02
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
CPC classification number: H05K1/0366 , H05K3/429 , H05K1/115 , H05K3/0047 , H05K2201/029
Abstract: An electronic printed circuit board structure for mitigating conductive anodic filament growth. The structure includes at least two conductive layers and a dielectric layer sandwiched between the conductive layers. At least one hole extends through the dielectric layer, and a layer of nonconductive material covers the at least one hole, wherein the nonconductive material is glass-free. A conductive plate layer is disposed over the nonconductive material layer to form a via connection in the structure.
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Patent Agency Ranking
公开(公告)号：US10378925B2
公开(公告)日：2019-08-13
申请号：US16162679
申请日：2018-10-17
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： William L. Brodsky , Silvio Dragone , Roger S. Krabbenhoft , David C. Long , Stefano S. Oggioni , Michael T. Peets , William Santiago-Fernandez
Abstract: Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.
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公开(公告)号：US10168185B2
公开(公告)日：2019-01-01
申请号：US14941908
申请日：2015-11-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： William L. Brodsky , Silvio Dragone , Roger S. Krabbenhoft , David C. Long , Stefano S. Oggioni , Michael T. Peets , William Santiago-Fernandez
Abstract: Methods of fabricating electronic circuits and electronic packages are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.
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公开(公告)号：US20170020005A1
公开(公告)日：2017-01-19
申请号：US14887364
申请日：2015-10-20
Applicant: International Business Machines Corporation
Inventor： Michael J. Fisher , Roger S. Krabbenhoft
IPC: H05K3/40
CPC classification number: H05K1/0203 , G06F21/72 , H03K19/00369 , H05K1/0272 , H05K1/0275 , H05K1/115 , H05K1/185 , H05K3/0044 , H05K3/4038 , H05K2201/10151
Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.
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公开(公告)号：US12207392B2
公开(公告)日：2025-01-21
申请号：US17933693
申请日：2022-09-20
Applicant: International Business Machines Corporation
Inventor： Matthew Doyle , David Clifford Long , Matteo Cocchini , Russell A. Budd , James Busby , Roger S. Krabbenhoft , Arthur J. Higby
Abstract: An electronic component includes a first trace configured to transmit a first signal and a second trace configured to transmit a second signal. The electronic component further includes a layer of conductive material separated from the first and second traces by a layer of insulative material. The electronic component further includes a first vertical wall formed in direct contact with the layer of conductive material. The electronic component further includes a second vertical wall formed in direct contact with the layer of conductive material. The second vertical wall is separated from the first vertical wall by a void, and the void extends between the first trace and the second trace.
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公开(公告)号：US09949357B2
公开(公告)日：2018-04-17
申请号：US14887364
申请日：2015-10-20
Applicant: International Business Machines Corporation
Inventor： Michael J. Fisher , Roger S. Krabbenhoft
IPC: H05K3/02 , H05K3/10 , H05K1/02 , H05K3/40 , H03K19/003 , G06F21/72 , H05K1/11 , H05K1/18 , H05K3/00
CPC classification number: H05K1/0203 , G06F21/72 , H03K19/00369 , H05K1/0272 , H05K1/0275 , H05K1/115 , H05K1/185 , H05K3/0044 , H05K3/4038 , H05K2201/10151
Abstract: The embodiments relate to a method for integrating a venting system in a circuit board. Three or more interconnected accesses (VIAs) are formed in a printed circuit board (PCB). The VIAs are interconnected by routing a bi-planar channel spanning through the VIAs. The channel includes at least two sections, including a first channel section at a first plane extending from the first VIA to the second VIA and a second channel section at a second plane extending from the second VIA to the third VIA. The first and second sections are at different planar levels.
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