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32 条记录 (耗时 0.036 秒)

    Light-emitting diode device geometry
    3.
    发明授权
    Light-emitting diode device geometry 失效
    发光二极管器件几何

    公开(公告)号：US06847052B2

    公开(公告)日：2005-01-25

    申请号：US10463219

    申请日：2003-06-17

    申请人： John C. C. Fan ,  Hong K. Choi ,  Tchang-Hun Oh ,  Jyh Chia Chen ,  Jagdish Narayan

    发明人： John C. C. Fan ,  Hong K. Choi ,  Tchang-Hun Oh ,  Jyh Chia Chen ,  Jagdish Narayan

    IPC分类号： H01L21/285 ,  H01L33/32 ,  H01L33/38 ,  H01L33/40 ,  H01L33/42 ,  H01L27/15 ,  H01L31/12 ,  H01L33/00

    CPC分类号： H01L33/40 ,  H01L21/28575 ,  H01L33/32 ,  H01L33/38 ,  H01L2933/0016 ,  Y10S257/918

    摘要： A semiconductor device includes: a substrate; an n-type semiconductor layer over the substrate, the n-type semiconductor layer having a planar top surface; a p-type semiconductor layer extending over a major portion of the n-type semiconductor layer and not extending over an exposed region of the n-type semiconductor layer located adjacent to at least one edge of the planar top surface of the n-type semiconductor layer; a first bonding pad provided on the exposed region of the n-type semiconductor layer; an electrode layer extending over the p-type semiconductor layer; and a second bonding pad on the electrode layer, the bonding pad including a central region for securing an electrical interconnect, and at least one finger-like region protruding from the central region, the finger-like region having a length extending away from the central region and a width that is substantially less than the length. A method for producing a semiconductor device also is described.

    摘要翻译： 半导体器件包括：衬底; 在该衬底上的n型半导体层，该n型半导体层具有平坦的顶表面; p型半导体层，其延伸在n型半导体层的主要部分上，并且不延伸在邻近n型半导体的平面顶表面的至少一个边缘的n型半导体层的暴露区域上 层; 设置在所述n型半导体层的所述露出区域上的第一焊盘; 在p型半导体层上延伸的电极层; 以及在所述电极层上的第二焊盘，所述焊盘包括用于固定电互连的中心区域和从所述中心区域突出的至少一个指状区域，所述指状区域具有远离所述中心部分的长度 区域和宽度明显小于长度。 还描述了一种半导体器件的制造方法。

    Bonding pad for gallium nitride-based light-emitting devices
    4.
    发明授权
    Bonding pad for gallium nitride-based light-emitting devices 失效
    用于氮化镓基发光器件的接合焊盘

    公开(公告)号：US07122841B2

    公开(公告)日：2006-10-17

    申请号：US10860798

    申请日：2004-06-03

    申请人： Tchang-Hun Oh ,  Hong K. Choi ,  John C. C. Fan ,  Jagdish Narayan

    发明人： Tchang-Hun Oh ,  Hong K. Choi ,  John C. C. Fan ,  Jagdish Narayan

    IPC分类号： H01L27/15

    CPC分类号： H01L29/452 ,  H01L21/28575 ,  H01L29/2003 ,  H01L33/32 ,  H01L33/40

    摘要： A semiconductor device includes a substrate having a first major surface; a semiconductor device structure over the first surface of the substrate, the device structure comprising an n-type semiconductor layer, and a p-type semiconductor layer over the n-type semiconductor layer; a p-side electrode having a first and a second surface, wherein the first surface is in electrical contact with the p-type semiconductor layer; and a p-side bonding pad over the p-side electrode. Preferably, the semiconductor device further comprises an n-side bonding pad over an n-type semiconductor layer. The p-side and n-side bonding pads each independently includes a gold layer as its top layer and a single or multiple layers of a diffusion barrier under the top gold layer. Optionally, one or more metal layers are further included under the diffusion barrier. Typically, the p-side bonding pad is formed on the p-side electrode. The n-side bonding pad typically is formed on the n-type semiconductor layer, and forms a good ohmic contact with the n-type semiconductor layer.

    摘要翻译： 半导体器件包括具有第一主表面的衬底; 在所述衬底的第一表面上的半导体器件结构，所述器件结构包括n型半导体层和在所述n型半导体层上的p型半导体层; 具有第一表面和第二表面的p侧电极，其中所述第一表面与所述p型半导体层电接触; 以及p侧电极上的p侧接合焊盘。 优选地，半导体器件还包括在n型半导体层上的n侧焊盘。 p侧和n侧接合焊盘各自独立地包括作为其顶层的金层和在顶部金层下方的单层或多层扩散阻挡层。 任选地，在扩散阻挡层下方还包括一个或多个金属层。 通常，p侧焊盘形成在p侧电极上。 n型接合焊盘通常形成在n型半导体层上，与n型半导体层形成良好的欧姆接触。

    Electrode for p-type gallium nitride-based semiconductors
    5.
    发明授权
    Electrode for p-type gallium nitride-based semiconductors 失效
    p型氮化镓基半导体电极

    公开(公告)号：US06734091B2

    公开(公告)日：2004-05-11

    申请号：US10187465

    申请日：2002-06-28

    申请人： Tchang-Hun Oh ,  Hong K. Choi ,  Bor-Yeu Tsaur ,  John C. C. Fan ,  Shirong Liao ,  Jagdish Narayan

    发明人： Tchang-Hun Oh ,  Hong K. Choi ,  Bor-Yeu Tsaur ,  John C. C. Fan ,  Shirong Liao ,  Jagdish Narayan

    IPC分类号： H01L2128

    CPC分类号： H01L33/42 ,  H01L21/28575 ,  H01L33/32

    摘要： An improved electrode for a p-type gallium nitride based semiconductor material is disclosed that includes a layer of an oxidized metal and a first and a second layer of a metallic material. The electrode is formed by depositing three or more metallic layers over the p-type semiconductor layer such that at least one metallic layer is in contact with the p-type semiconductor layer. At least two of the metallic layers are then subjected to an annealing treatment in the presence of oxygen to oxidize at least one of the metallic layers to form a metal oxide. The electrodes provide good ohmic contacts to p-type gallium nitride-based semiconductor materials and, thus, lower the operating voltage of gallium nitride-based semiconductor devices.

    摘要翻译： 公开了一种用于p型氮化镓基半导体材料的改进的电极，其包括氧化金属层和金属材料的第一和第二层。 电极通过在p型半导体层上沉积三个或更多个金属层而形成，使得至少一个金属层与p型半导体层接触。 然后至少两个金属层在氧的存在下进行退火处理以氧化至少一个金属层以形成金属氧化物。 电极为p型氮化镓基半导体材料提供良好的欧姆接触，从而降低氮化镓基半导体器件的工作电压。

    Dislocation density reduction in gallium arsenide on silicon heterostructures
    9.
    发明授权
    Dislocation density reduction in gallium arsenide on silicon heterostructures 失效
    硅异质结构中砷化镓的位错密度降低

    公开(公告)号：US5208182A

    公开(公告)日：1993-05-04

    申请号：US790356

    申请日：1991-11-12

    申请人： Jagdish Narayan ,  John C. C. Fan

    发明人： Jagdish Narayan ,  John C. C. Fan

    IPC分类号： H01L21/20 ,  H01L21/324

    CPC分类号： H01L21/3245 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/0262 ,  Y10S148/16 ,  Y10S438/933 ,  Y10S438/938

    摘要： A method of forming gallium arsenide on silicon heterostructure including the use of strained layer superlattices in combination with rapid thermal annealing to achieve a reduced threading dislocation density in the epilayers. Strain energy within the superlattices causes threading dislocations to bend, preventing propagation through the superlattices to the epilayer. Rapid thermal annealing causes extensive realignment and annihilation of dislocations of opposite Burgers vectors and a further reduction of threading dislocations in the epilayer.

    摘要翻译： 一种在硅异质结构上形成砷化镓的方法，包括使用应变层超晶格与快速热退火相结合，以实现外延层中的穿透位错密度降低。 超晶格内的应变能导致穿透位错弯曲，防止通过超晶格传播到外延层。 快速热退火导致相反的汉堡载体的位错的广泛重排和消除，并进一步减少外延层中的穿线位错。

    Growth and integration of epitaxial gallium nitride films with silicon-based devices
    10.
    发明申请
    Growth and integration of epitaxial gallium nitride films with silicon-based devices 有权
    外延氮化镓薄膜与硅基器件的生长和集成

    公开(公告)号：US20050124161A1

    公开(公告)日：2005-06-09

    申请号：US10970773

    申请日：2004-10-21

    申请人： Thomas Rawdanowicz ,  Jagdish Narayan

    发明人： Thomas Rawdanowicz ,  Jagdish Narayan

    IPC分类号： C30B23/02 ,  C30B25/18 ,  C30B29/40 ,  H01L21/338 ,  H01L21/302 ,  H01L21/461

    CPC分类号： C30B25/18 ,  C30B23/02 ,  C30B29/40 ,  H01L21/8258

    摘要： Epitaxial gallium nitride is grown on a silicon substrate while reducing or suppressing the formation of a buffer layer. The gallium nitride may be grown directly on the silicon substrate, for example using domain epitaxy. Alternatively, less than one complete monolayer of silicon nitride may be formed between the silicon and the gallium nitride. Subsequent to formation of the gallium nitride, an interfacial layer of silicon nitride may be formed between the silicon and the gallium nitride.

    摘要翻译： 在减少或抑制缓冲层的形成的同时，在硅衬底上生长外延氮化镓。 可以直接在硅衬底上生长氮化镓，例如使用畴外延。 或者，可以在硅和氮化镓之间形成少于一个完整的氮化硅单层。 在形成氮化镓之后，可以在硅和氮化镓之间形成氮化硅的界面层。