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    Lateral diffusion field effect transistor with asymmetric gate dielectric profile
    4.
    发明授权
    Lateral diffusion field effect transistor with asymmetric gate dielectric profile 有权
    具有不对称栅极电介质轮廓的侧向扩散场效应晶体管

    公开(公告)号：US07829945B2

    公开(公告)日：2010-11-09

    申请号：US11924650

    申请日：2007-10-26

    申请人： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

    发明人： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

    IPC分类号： H01L21/331

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/512 ,  H01L29/66659

    摘要： A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.

    摘要翻译： 在半导体基板上形成包括均匀厚度的栅极电介质，栅电极和耐氧扩散栅极盖的栅极堆叠。 仅在栅电极的漏极侧进行热氧化，同时防止源极侧受热氧化。 栅电极的漏极侧壁上的热氧化物与层状厚度的含氧化硅的栅极电介质整体形成，其厚度从源极侧向漏极侧单调增加。 厚度分布可以与栅电极的漏极侧边缘自对准，或者可以具有自限制厚度的部分。 梯度厚度分布可以有利地用于形成提供增强性能的横向扩散金属氧化物半导体场效应晶体管。

    LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE
    5.
    发明申请
    LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE 有权
    具有不对称栅介质剖面的横向扩散场效应晶体管

    公开(公告)号：US20090108347A1

    公开(公告)日：2009-04-30

    申请号：US11924650

    申请日：2007-10-26

    申请人： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

    发明人： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/512 ,  H01L29/66659

    摘要： A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.

    摘要翻译： 在半导体基板上形成包括均匀厚度的栅极电介质，栅电极和耐氧扩散栅极盖的栅极堆叠。 仅在栅电极的漏极侧进行热氧化，同时防止源极侧受热氧化。 栅电极的漏极侧壁上的热氧化物与层状厚度的含氧化硅的栅极电介质整体形成，其厚度从源极侧向漏极侧单调增加。 厚度分布可以与栅电极的漏极侧边缘自对准，或者可以具有自限制厚度的部分。 梯度厚度分布可以有利地用于形成提供增强性能的横向扩散金属氧化物半导体场效应晶体管。

    POWER CLAMP DEVICES WITH VERTICAL NPN DEVICES
    7.
    发明申请
    POWER CLAMP DEVICES WITH VERTICAL NPN DEVICES 审中-公开
    具有垂直NPN器件的电源钳位器件

    公开(公告)号：US20080002316A1

    公开(公告)日：2008-01-03

    申请号：US11427063

    申请日：2006-06-28

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Steven H. Voldman

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Steven H. Voldman

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0285

    摘要： ESD power clamp devices with vertical NPN devices are disclosed. The power clamp is formed on an N type substrate and includes an N channel field effect transistor (NFET). The source and drain regions of the NFET, a P type epitaxial region under the NFET, and the N type substrate constitutes two vertical NPN devices. As such, vertical interactions of electrons are enabled to avoid the disadvantages of traditional power clamps, e.g., minority carrier cross-talk.

    摘要翻译： 公开了具有垂直NPN器件的ESD功率钳位器件。 电源钳位形成在N型衬底上并且包括N沟道场效应晶体管（NFET）。 NFET的源极和漏极区域，NFET下的P型外延区域和N型衬底构成两个垂直NPN器件。 因此，电子的垂直相互作用能够避免传统功率钳位的缺点，例如少数载流子串扰。

    Methods for forming anti-reflection structures for CMOS image sensors
    9.
    发明授权
    Methods for forming anti-reflection structures for CMOS image sensors 有权
    CMOS图像传感器形成抗反射结构的方法

    公开(公告)号：US08003425B2

    公开(公告)日：2011-08-23

    申请号：US12120459

    申请日：2008-05-14

    申请人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

    发明人： James W. Adkisson ,  John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Charles F. Musante

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14685 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14689 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Protuberances, having vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode, are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sublithographic features of a first polymeric block component within a matrix of a second polymeric block component. The pattern of the polymeric block component is transferred into a first optical layer to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

    摘要翻译： 在具有不同折射率的两层之间的光学界面处形成具有小于由光电二极管可检测的光的波长范围的垂直和横向尺寸的突起。 突起可以通过采用在第二聚合物嵌段组分的基质内形成第一聚合物嵌段组分的亚光刻特征阵列的自组装嵌段共聚物来形成。 聚合物嵌段组分的图案被转移到第一光学层中以形成纳米级突起的阵列。 或者，可以使用常规光刻来形成尺寸小于光的波长的突起。 第二光学层直接形成在第一光学层的突起上。 第一和第二光学层之间的界面具有渐变的折射率，并提供很少的反射光的高透射率。

    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
    10.
    发明授权
    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
    具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法

    公开(公告)号：US07772028B2

    公开(公告)日：2010-08-10

    申请号：US11959841

    申请日：2007-12-19

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L21/66

    CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。