公开(公告)号：US20130134581A1

公开(公告)日：2013-05-30

申请号：US13308162

申请日：2011-11-30

申请人： Jing-Cheng LIN ,  Po-Hao TSAI

发明人： Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H01L23/498 ,  H01L21/50 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1401 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.

摘要翻译： 用于形成凸块结构的机构减少了芯片和封装衬底之间的间隙的变化。 通过在电镀后对芯片和/或基板上的凸块结构上的焊料层进行平坦化，可以控制凸块结构的高度，以最小化晶片内部以及晶片位置，图案密度，晶粒尺寸和工艺变化中的变化。 结果，芯片和基板之间的间隔被控制得更均匀。 因此，底部填充质量得到改善。

公开(公告)号：US20130223014A1

公开(公告)日：2013-08-29

申请号：US13403511

申请日：2012-02-23

申请人： Jing-Cheng LIN ,  Po-Hao TSAI

发明人： Jing-Cheng LIN ,  Po-Hao TSAI

IPC分类号： H05K7/00 ,  B23K31/02

CPC分类号： H01L24/11 ,  B23K1/0016 ,  B23K2101/42 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： The mechanisms for forming bumps on packaged dies and package substrates reduce variation of bump heights across the packaged dies and packaged substrates. Bumps are designed to have different widths to counter the higher plating current near edge(s) of dies or substrates. Bump sizes can be divided into different zones depending on the bump patterns and densities across the packaged die and/or substrates. Smaller bumps near edges reduce the thickness of plated film(s), which would have been thicker due to being near the edges. As a result, the bump heights across the packaged dies and/or substrates can be kept significantly constant and chip package can be properly formed.

摘要翻译： 用于在封装的芯片和封装衬底上形成凸点的机制减少了封装的裸片和封装的衬底上的凸起高度的变化。 冲击波被设计成具有不同的宽度以抵抗在模具或基底的边缘附近的较高电镀电流。 凸起尺寸可以分为不同的区域，这取决于包装模具和/或基底上的凸起图案和密度。 边缘附近的较小的凸起减小了镀膜的厚度，这将由于靠近边缘而变厚。 结果，穿过封装的管芯和/或衬底的突起高度可以保持显着恒定，并且可以适当地形成芯片封装。

公开(公告)号：US20130026620A1

公开(公告)日：2013-01-31

申请号：US13192756

申请日：2011-07-28

申请人： Cheng-Lin HUANG ,  I-Ting CHEN ,  Ying Ching SHIH ,  Po-Hao TSAI ,  Szu Wei LU ,  Jing-Cheng LIN ,  Shin-Puu JENG ,  Chen-Hua YU

发明人： Cheng-Lin HUANG ,  I-Ting CHEN ,  Ying Ching SHIH ,  Po-Hao TSAI ,  Szu Wei LU ,  Jing-Cheng LIN ,  Shin-Puu JENG ,  Chen-Hua YU

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/14 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0346 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/13011 ,  H01L2224/13014 ,  H01L2224/13078 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1405 ,  H01L2224/14051 ,  H01L2224/145 ,  H01L2224/16238 ,  H01L2224/17107 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01083 ,  H01L2924/01053 ,  H01L2924/01079 ,  H01L2924/01051 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The disclosure relates to a conductive bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface and conductive bumps distributed over the major surface of the substrate. Each of a first subset of the conductive bumps comprise a regular body, and each of a second subset of the conductive bumps comprise a ring-shaped body.

摘要翻译： 本发明涉及半导体器件的导电凸块结构。 半导体器件的示例性结构包括包括主表面的衬底和分布在衬底的主表面上的导电凸块。 导电凸块的第一子集中的每一个包括规则体，并且导电凸块的第二子集中的每一个包括环形体。