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315 条记录 (耗时 0.053 秒)

    Modular substrate processing system
    1.
    发明授权
    Modular substrate processing system 失效
    模块化基板处理系统

    公开(公告)号：US06235634B1

    公开(公告)日：2001-05-22

    申请号：US09082483

    申请日：1998-05-20

    申请人： John M. White ,  Robert B. Conner ,  Kam S. Law ,  Norman L. Turner ,  William T. Lee ,  Shinichi Kurita

    发明人： John M. White ,  Robert B. Conner ,  Kam S. Law ,  Norman L. Turner ,  William T. Lee ,  Shinichi Kurita

    IPC分类号： H01L2144

    CPC分类号： H01L21/67167 ,  H01L21/67161 ,  H01L21/67173 ,  H01L21/67236 ,  H01L21/67721 ,  H01L21/67727 ,  H01L21/67736 ,  H01L21/68707

    摘要： The invention provides an apparatus and method for performing a process on a substrate. At least two types of structures may be used to provide a flow path for a substrate so that the substrate may be moved from one processing or loading position to another. The first is a conveyor. The second is a track. The flow path may be a closed continuous loop. Each processing island has a valve for introduction and extraction of the substrate into and out of an interior of the island. The processing island may include load locks, and may include in conjunction therewith an inspection station, a CVD chamber, a PECVD chamber, a PVD chamber, a post-anneal chamber, a cleaning chamber, a descumming chamber, an etch chamber, or a combination of such chambers.

    摘要翻译： 本发明提供了一种在衬底上进行处理的装置和方法。 可以使用至少两种类型的结构来提供用于衬底的流动路径，使得衬底可以从一个处理或装载位置移动到另一个。 第一个是输送机。 第二是轨道。 流动路径可以是闭合的连续环路。 每个处理岛具有用于将基板引入和提取到岛内部的阀。 处理岛可以包括负载锁，并且可以包括检查站，CVD室，PECVD室，PVD室，后退火室，清洁室，除污室，蚀刻室或 这些室的组合。

    Method and apparatus for metallization of large area substrates
    4.
    发明授权
    Method and apparatus for metallization of large area substrates 失效
    用于大面积基板金属化的方法和装置

    公开(公告)号：US07029529B2

    公开(公告)日：2006-04-18

    申请号：US10247403

    申请日：2002-09-19

    申请人： Kam S. Law ,  Robert Z. Bachrach ,  John M. White ,  Quanyuan Shang

    发明人： Kam S. Law ,  Robert Z. Bachrach ,  John M. White ,  Quanyuan Shang

    IPC分类号： B05C1/02 ,  B05C13/02

    CPC分类号： C23C18/1632 ,  B05D1/002 ,  B05D7/142 ,  C23C18/1605 ,  C23C18/1608 ,  H01L21/288 ,  H01L21/76838 ,  H05K3/12 ,  H05K3/182

    摘要： A system and method for processing large area substrates. In one embodiment, a system for processing large area substrates includes prep station, a stamping station and a stamp that is automatically moved between the stamping station and the prep station. The stamping station is adapted to retain a large area substrate thereon. The stamp has a patterned bottom surface that is adapted for microcontact printing. The prep station is for applying a precursor to the patterned bottom surface of the stamp. In one embodiment, a method for processing large area substrates includes the steps of disposing a large area substrate on a platen, inking a stamp adapted for microcontact printing, and automatically contacting a bottom of the stamp to the large area substrate supported on a platen.

    摘要翻译： 一种用于处理大面积基板的系统和方法。 在一个实施例中，用于处理大面积基板的系统包括准备台，冲压站和在冲压站和准备站之间自动移动的印模。 冲压站适于在其上保持大面积的基板。 印模具有适于微接触印刷的图案底面。 准备站用于将前体施加到印模的图案化底表面。 在一个实施例中，一种用于处理大面积衬底的方法包括以下步骤：将大面积衬底设置在压板上，上墨适用于微接触印刷，以及自动地将印模底部接触到支撑在压板上的大面积衬底。

    Optical integrated circuits (ICs)
    6.
    发明授权
    Optical integrated circuits (ICs) 有权
    光集成电路（IC）

    公开(公告)号：US07087179B2

    公开(公告)日：2006-08-08

    申请号：US09734950

    申请日：2000-12-11

    申请人： Cecilia Y. Mak ,  John M. White ,  Kam S. Law ,  Dan Maydan

    发明人： Cecilia Y. Mak ,  John M. White ,  Kam S. Law ,  Dan Maydan

    IPC分类号： B29D11/00

    CPC分类号： G02B6/12004 ,  G02B6/13 ,  G02B6/132

    摘要： In one aspect, the invention provides methods and apparatus for forming optical devices on large area substrates. The large area substrates are preferably made of quartz, silica or fused silica. The large area substrates enable larger optical devices to be formed on a single die. In another aspect, the invention provides methods and apparatus for forming integrated optical devices on large area substrates, such as quartz, silica or fused silica substrates. In another aspect, the invention provides methods and apparatus for forming optical devices using damascene techniques on large area substrates or silicon substrates. In another aspect, methods for forming optical devices by bonding an upper cladding layer on a lower cladding and a core is provided.

    摘要翻译： 一方面，本发明提供了用于在大面积基板上形成光学装置的方法和装置。 大面积基板优选由石英，二氧化硅或熔融二氧化硅制成。 大面积基板使得能够在单个管芯上形成更大的光学器件。 另一方面，本发明提供了用于在大面积衬底（例如石英，二氧化硅或熔融二氧化硅衬底）上形成集成光学器件的方法和装置。 在另一方面，本发明提供了使用大面积衬底或硅衬底上的镶嵌技术形成光学器件的方法和装置。 在另一方面，提供了通过将下包层和芯上的上包层结合来形成光器件的方法。

    Film deposition using a finger type shadow frame
    7.
    发明授权
    Film deposition using a finger type shadow frame 有权
    使用手指型阴影框的胶片沉积

    公开(公告)号：US06355108B1

    公开(公告)日：2002-03-12

    申请号：US09338245

    申请日：1999-06-22

    申请人： Tae Kyung Won ,  Quanyuan Shang ,  Robert M. Robertson ,  Soo Young Choi ,  Kam S. Law ,  Robert I. Greene ,  John M. White

    发明人： Tae Kyung Won ,  Quanyuan Shang ,  Robert M. Robertson ,  Soo Young Choi ,  Kam S. Law ,  Robert I. Greene ,  John M. White

    IPC分类号： C23C1600

    CPC分类号： C23C16/24 ,  C23C16/345 ,  C23C16/4583 ,  C23C16/4585 ,  H01J37/32623

    摘要： The present invention relates generally to a clamping and alignment assembly for a substrate processing system. The clamping and aligning assembly generally includes a shadow frame, a floating plasma shield and a plurality of insulating alignment pins. The shadow frame comprises a plurality of tabs extending inwardly therefrom and is shaped to accommodate a substrate. The tabs comprise protruding contact surfaces for stabilizing a substrate on a support member during processing. The insulating alignment pins are disposed at a perimeter of a movable support member and cooperate with an alignment recess formed in the shadow frame to urge the shadow frame into a desired position. Preferably, the floating plasma shield is disposed on the insulating alignment pins in spaced relationship between the support member and the shadow frame to shield the perimeter of the support member during processing.

    摘要翻译： 本发明一般涉及用于衬底处理系统的夹紧和对准组件。 夹持和对准组件通常包括阴影框架，浮动等离子体屏蔽件和多个绝缘对准销钉。 阴影框架包括从其向内延伸的多个突片，并且成形为容纳衬底。 突片包括用于在加工期间稳定支撑构件上的基板的突出接触表面。 绝缘对准销布置在可移动支撑构件的周边处，并与形成在阴影框架中的对准凹槽配合，以将阴影框架推动到期望的位置。 优选地，浮动等离子体屏蔽以间隔开的关系设置在绝缘对准销上，在支撑构件和阴影框架之间，以在加工期间屏蔽支撑构件的周边。

    Process for PECVD of silicon oxide using TEOS decomposition
    8.
    再颁专利
    Process for PECVD of silicon oxide using TEOS decomposition 失效

    公开(公告)号：USRE36623E

    公开(公告)日：2000-03-21

    申请号：US752972

    申请日：1996-12-02

    申请人： David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    发明人： David Nin-Kou Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC分类号： C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/509 ,  C23C16/54 ,  H01L21/314 ,  H01L21/316 ,  H05H1/24

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surface. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the sane reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

    Plasma-enhanced CVD process using TEOS for depositing silicon oxide
    9.
    发明授权
    Plasma-enhanced CVD process using TEOS for depositing silicon oxide 失效

    公开(公告)号：US5362526A

    公开(公告)日：1994-11-08

    申请号：US645999

    申请日：1991-01-23

    申请人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    发明人： David N. Wang ,  John M. White ,  Kam S. Law ,  Cissy Leung ,  Salvador P. Umotoy ,  Kenneth S. Collins ,  John A. Adamik ,  Ilya Perlov ,  Dan Maydan

    IPC分类号： C23C16/48 ,  C23C16/04 ,  C23C16/40 ,  C23C16/42 ,  C23C16/44 ,  C23C16/455 ,  C23C16/46 ,  C23C16/50 ,  C23C16/509 ,  C23C16/54 ,  C23F4/00 ,  C30B25/14 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/683 ,  B05D3/06

    CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/455 ,  C23C16/45521 ,  C23C16/5096 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/3244 ,  H01L21/31604

    摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.