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22 条记录 (耗时 0.018 秒)

    Complementary inductor structures
    3.
    发明申请
    Complementary inductor structures 审中-公开
    互补电感结构

    公开(公告)号：US20070146105A1

    公开(公告)日：2007-06-28

    申请号：US11320942

    申请日：2005-12-28

    申请人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

    发明人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

    IPC分类号： H01F1/00

    CPC分类号： H01F17/0006 ,  H01F27/346 ,  H01F27/38 ,  H01F2017/0046 ,  H01F2017/0073 ,  H01F2017/008

    摘要： Complementary inductor structures. The inductor structure may include two or more sub-inductors that have positive coupling to provide a total inductance approximately equal to the sum of the inductance provided by the two or more sub-inductors. Radiation from the two or more sub-inductors may be in different phases to partially, or even totally, cancel and result in a reduced overall radiation, which may reduce electromagnetic interference and/or electromagnetic coupling.

    摘要翻译： 互补电感结构。 电感器结构可以包括具有正耦合的两个或更多个子电感器，以提供大致等于由两个或多个子电感器提供的电感之和的总电感。 来自两个或更多个子电感器的辐射可以处于不同的相位以部分或甚至完全消除并导致减小的总辐射，这可以减少电磁干扰和/或电磁耦合。

    Multi-chip assembly with optically coupled die
    4.
    发明申请
    Multi-chip assembly with optically coupled die 有权
    具有光耦合模的多芯片组装

    公开(公告)号：US20070102733A1

    公开(公告)日：2007-05-10

    申请号：US11270271

    申请日：2005-11-09

    申请人： Qing Zhou ,  Daoqiang Lu ,  Jiangqi He ,  Wei Shi ,  Xiang Zeng

    发明人： Qing Zhou ,  Daoqiang Lu ,  Jiangqi He ,  Wei Shi ,  Xiang Zeng

    IPC分类号： H01L29/768

    CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L2924/00014 ,  H01L2224/48

    摘要： Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

    摘要翻译： 公开了包括光耦合管芯的多芯片组件的实施例。 多芯片组件可以包括两个相对的基板，并且在每个基板上安装多个管芯。 一个基板上的至少一个管芯与另一个基板上的至少一个相对的管芯光学连通。 描述和要求保护其他实施例。

    DATA SIGNAL INTERCONNECTION WITH REDUCED CROSSTALK
    7.
    发明申请
    DATA SIGNAL INTERCONNECTION WITH REDUCED CROSSTALK 有权
    数据信号互连与降低CROSSTALK

    公开(公告)号：US20070155195A1

    公开(公告)日：2007-07-05

    申请号：US11324040

    申请日：2005-12-30

    申请人： Jiangqi He ,  BaoShu Xu ,  Xiang Zeng

    发明人： Jiangqi He ,  BaoShu Xu ,  Xiang Zeng

    IPC分类号： H01R12/00

    CPC分类号： H01R13/6461 ,  H01R13/6477 ,  Y10S439/941

    摘要： Data signal interconnections are described that offer reduced cross talk particularly with high speed differential signaling. In one example, the invention includes a plurality of interconnects to carry data signals between a first component and a second component, the plurality of interconnects including a first set of interconnects oriented in a first direction and a second set of interconnects oriented in a second direction, different from the first direction

    摘要翻译： 描述了数据信号互连，其提供减少的串扰，特别是与高速差分信号。 在一个示例中，本发明包括在第一组件和第二组件之间承载数据信号的多个互连，所述多个互连包括在第一方向上定向的第一组互连和在第二方向上定向的第二组互连 ，不同于第一个方向

    Packaged spiral inductor structures, processes of making same, and systems containing same
    8.
    发明申请
    Packaged spiral inductor structures, processes of making same, and systems containing same 有权
    封装的螺旋电感器结构，制造方法以及含有它们的系统

    公开(公告)号：US20070152796A1

    公开(公告)日：2007-07-05

    申请号：US11323339

    申请日：2005-12-30

    申请人： Jiangqi He ,  Robert Sankman ,  BaoShu Xu ,  Xiang Zeng

    发明人： Jiangqi He ,  Robert Sankman ,  BaoShu Xu ,  Xiang Zeng

    IPC分类号： H01F27/28

    CPC分类号： H01F17/0006 ,  H01F27/323 ,  H01F41/041 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A spiral inductor is disposed above a substrate that includes two different materials. A dielectric film is the first material that provides structural integrity for the substrate. A second dielectric is the second material that provides a low dielectric-constant (low-K) material closest to the spiral inductor coil. A process of forming the spiral inductor includes patterning the substrate to allow a recess as a receptacle for the second dielectric, followed by forming the spiral inductor mostly above the second dielectric.

    摘要翻译： 螺旋电感器设置在包括两种不同材料的衬底之上。 电介质膜是为衬底提供结构完整性的第一种材料。 第二介质是提供最接近螺旋电感线圈的低介电常数（低K）材料的第二材料。 形成螺旋电感器的过程包括图案化衬底以允许凹槽作为用于第二电介质的插座，随后形成主要位于第二电介质上方的螺旋电感器。

    IC package with signal land pads
    9.
    发明申请
    IC package with signal land pads 有权
    IC封装带信号焊盘

    公开(公告)号：US20060180905A1

    公开(公告)日：2006-08-17

    申请号：US11060104

    申请日：2005-02-16

    申请人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

    发明人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

    IPC分类号： H01L23/02 ,  H01L23/12 ,  H01L23/34

    CPC分类号： H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15313

    摘要： In one embodiment, an integrated circuit package comprises a substrate including a first surface having a plurality of signal land pads and a second surface having a plurality of signal die pads; a plurality of signal connectors arranged to electrically couple the plurality of the signal land pads to the plurality of the signal die pads; and a ground plane, disposed in an adjacent, spaced-apart relationship to the plurality of signal land pads. The ground plane includes a plurality of holes with at least one of the holes having at least one of the signal connectors extending therethrough and being dimensioned and configured approximately to be as large or larger than at least one of the signal land pads disposed adjacent to the at least one hole.

    摘要翻译： 在一个实施例中，集成电路封装包括：衬底，其包括具有多个信号焊盘的第一表面和具有多个信号管芯焊盘的第二表面; 多个信号连接器，其布置成将多个信号焊盘区电耦合到多个信号管芯焊盘; 以及接地平面，与多个信号焊盘相邻设置成间隔开的关系。 接地平面包括多个孔，其中至少一个孔具有延伸穿过其中的信号连接器中的至少一个，其尺寸和构造近似大于或大于与邻近 至少有一个洞。

    Reducing parasitic mutual capacitances
    10.
    发明申请
    Reducing parasitic mutual capacitances 有权
    减少寄生互电容

    公开(公告)号：US20070001260A1

    公开(公告)日：2007-01-04

    申请号：US11174246

    申请日：2005-06-30

    申请人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

    发明人： Xiang Zeng ,  Jiangqi He ,  BaoShu Xu

    IPC分类号： H01L23/12 ,  H01L21/00

    CPC分类号： H01G4/33 ,  H01G4/236 ,  H01G4/38 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/3025 ,  H05K1/162

    摘要： A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

    摘要翻译： 一种降低嵌入式无源器件中寄生互电容的方法。 第一电容器由嵌入电介质层的第一和第二电极形成。 第二电容器由嵌入电介质层的第三电极和第四电极形成。 从第一金属层蚀刻第三和第一电极。 从第二金属层蚀刻第四和第二电极。 第一和第四电极通过介电层的连接来连接，以屏蔽第一和第二电容器之间的互电容。