公开(公告)号：US4946547A

公开(公告)日：1990-08-07

申请号：US421375

申请日：1989-10-13

申请人： John W. Palmour ,  Hua-Shuang Kong ,  John A. Edmond

发明人： John W. Palmour ,  Hua-Shuang Kong ,  John A. Edmond

IPC分类号： H01L21/205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/36 ,  H01L21/465

CPC分类号： H01L21/02529 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02609 ,  H01L21/02631 ,  H01L21/02658 ,  H01L21/465

摘要： The invention is a method of forming a substantially planar surface on a monocrystalline silicon carbide crystal by exposing the substantially planar surface to an etching plasma until any surface or subsurface damage caused by any mechanical preparation of the surface is substantially removed. The etch is limited, however, to a time period less than that over which the plasma etch will develop new defects in the surface or aggravate existing ones, and while using a plasma gas and electrode system that do not themselves aggravate or cause substantial defects in the surface.

摘要翻译： 本发明是通过将基本上平坦的表面暴露于蚀刻等离子体，直到基本上除去由表面的任何机械制备引起的任何表面或地下损伤为止，在单晶碳化硅晶体上形成基本平坦的表面的方法。 然而，蚀刻被限制到比等离子体蚀刻将在表面上产生新缺陷或加剧现有蚀刻的时间段，并且在使用本身不加重或引起实质缺陷的等离子体气体和电极系统的时候 表面。

公开(公告)号：US5539217A

公开(公告)日：1996-07-23

申请号：US103866

申请日：1993-08-09

申请人： John A. Edmond ,  John W. Palmour

发明人： John A. Edmond ,  John W. Palmour

IPC分类号： H01L29/744 ,  H01L29/24 ,  H01L29/74 ,  H01L31/0312 ,  H01L31/111

CPC分类号： H01L29/1608 ,  H01L29/74

摘要： The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.

摘要翻译： SiC晶闸管具有衬底，阳极，漂移区，栅极和阴极。 衬底，阳极，漂移区，栅极和阴极各自优选由碳化硅形成。 基板由具有一种导电类型的碳化硅形成，并且根据实施例，阳极或阴极与基板相邻地形成并且具有与基板相同的导电类型。 邻近阳极或阴极形成碳化硅的漂移区，并且具有与阳极或阴极相反的导电类型。 根据实施例，也形成在漂移区域或阴极附近的栅极，并且具有与漂移区域或阴极相反的导电类型。 再次取决于实施例的阳极或阴极形成在栅极或漂移区域附近并且具有与栅极相反的导电类型。

公开(公告)号：US4945394A

公开(公告)日：1990-07-31

申请号：US113692

申请日：1987-10-26

申请人： John W. Palmour ,  John A. Edmond

发明人： John W. Palmour ,  John A. Edmond

IPC分类号： H01L29/24 ,  H01L29/732

CPC分类号： H01L29/1608 ,  H01L29/732 ,  Y10S438/931

摘要： The invention comprises a bipolar junction transistor formed in silicon carbide. By utilizing high temperature ion implantation of doping ions, the base and emitter can be formed as wells, resulting in a planar transistor. Mesa-type transistors are also disclosed.

摘要翻译： 本发明包括在碳化硅中形成的双极结型晶体管。 通过利用掺杂离子的高温离子注入，基极和发射极可以形成为阱，从而形成平面晶体管。 还公开了Mesa型晶体管。

公开(公告)号：US06972436B2

公开(公告)日：2005-12-06

申请号：US09878442

申请日：2001-06-11

申请人： Mrinal Kanti Das ,  Lori A. Lipkin ,  John W. Palmour ,  Scott Sheppard ,  Helmut Hagleitner

发明人： Mrinal Kanti Das ,  Lori A. Lipkin ,  John W. Palmour ,  Scott Sheppard ,  Helmut Hagleitner

IPC分类号： H01L29/749 ,  H01G4/33 ,  H01L21/02 ,  H01L21/04 ,  H01L21/28 ,  H01L21/314 ,  H01L21/329 ,  H01L21/336 ,  H01L21/338 ,  H01L21/822 ,  H01L27/04 ,  H01L27/08 ,  H01L29/06 ,  H01L29/12 ,  H01L29/161 ,  H01L29/24 ,  H01L29/40 ,  H01L29/51 ,  H01L29/739 ,  H01L29/78 ,  H01L29/812 ,  H01L29/861 ,  H01L29/94 ,  H01L31/0312 ,  H01L29/76

CPC分类号： H01L29/7802 ,  H01G4/1272 ,  H01G4/20 ,  H01G4/33 ,  H01L21/045 ,  H01L21/049 ,  H01L27/0805 ,  H01L28/40 ,  H01L29/1608 ,  H01L29/408 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/8611 ,  H01L29/94

摘要： Capacitors and interconnection structures for silicon carbide are provided having an oxide layer, a layer of dielectric material and a second oxide layer on the layer of dielectric material. The thickness of the oxide layers may be from about 0.5 to about 33 percent of the thickness of the oxide layers and the layer of dielectric material. Capacitors and interconnection structures for silicon carbide having silicon oxynitride layer as a dielectric structure are also provided. Such a dielectric structure may be between metal layers to provide a metal-insulator-metal capacitor or may be used as a inter-metal dielectric of an interconnect structure so as to provide devices and structures having improved mean time to failure. Methods of fabricating such capacitors and structures are also provided.

摘要翻译： 提供了碳化硅的电容器和互连结构，其具有氧化物层，电介质材料层和介电材料层上的第二氧化物层。 氧化物层的厚度可以是氧化物层的厚度和电介质材料层的约0.5至约33％。 还提供了具有氧氮化硅层作为电介质结构的碳化硅的电容器和互连结构。 这种介电结构可以在金属层之间，以提供金属 - 绝缘体 - 金属电容器，或者可以用作互连结构的金属间介质，从而提供具有改善的平均故障时间的装置和结构。 还提供了制造这种电容器和结构的方法。

公开(公告)号：US06956238B2

公开(公告)日：2005-10-18

申请号：US09911995

申请日：2001-07-24

申请人： Sei-Hyung Ryu ,  Anant Agarwal ,  Mrinal Kanti Das ,  Lori A. Lipkin ,  John W. Palmour ,  Ranbir Singh

发明人： Sei-Hyung Ryu ,  Anant Agarwal ,  Mrinal Kanti Das ,  Lori A. Lipkin ,  John W. Palmour ,  Ranbir Singh

IPC分类号： H01L21/04 ,  H01L21/336 ,  H01L29/10 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  H01L29/161

CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/7838

摘要： Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) and methods of fabricating silicon carbide MOSFETs are provided. The silicon carbide MOSFETs have an n-type silicon carbide drift layer, spaced apart p-type silicon carbide regions in the n-type silicon carbide drift layer and having n-type silicon carbide regions therein, and a nitrided oxide layer. The MOSFETs also have n-type shorting channels extending from respective ones of the n-type silicon carbide regions through the p-type silicon carbide regions to the n-type silicon carbide drift layer. In further embodiments, silicon carbide MOSFETs and methods of fabricating silicon carbide MOSFETs are provided that include a region that is configured to self-deplete the source region, between the n-type silicon carbide regions and the drift layer, adjacent the oxide layer, upon application of a zero gate bias.

摘要翻译： 提供了碳化硅金属氧化物半导体场效应晶体管（MOSFET）和制造碳化硅MOSFET的方法。 碳化硅MOSFET具有n型碳化硅漂移层，n型碳化硅漂移层中间隔开的p型碳化硅区域，其中具有n型碳化硅区域和氮化氧化物层。 MOSFET还具有从n型碳化硅区域中的相应的n型碳化硅区域延伸穿过p型碳化硅区域到n型碳化硅漂移层的n型短路通道。 在另外的实施例中，提供了碳化硅MOSFET和制造碳化硅MOSFET的方法，其包括被配置为在n型碳化硅区域和与氧化物层相邻的漂移层之间自耗光源区域的区域 零门偏置的应用。

公开(公告)号：US06514779B1

公开(公告)日：2003-02-04

申请号：US09981523

申请日：2001-10-17

申请人： Sei-Hyung Ryu ,  Anant Agarwal ,  Craig Capell ,  John W. Palmour

发明人： Sei-Hyung Ryu ,  Anant Agarwal ,  Craig Capell ,  John W. Palmour

IPC分类号： G01R3126

CPC分类号： G01R31/2831 ,  H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

摘要： A silicon carbide device is fabricated by forming a plurality of a same type of silicon carbide devices on at least a portion of a silicon carbide wafer in a predefined pattern. The silicon carbide devices have corresponding first contacts on a first face of the silicon carbide wafer. The plurality of silicon carbide devices are electrically, tested to identify ones of the plurality of silicon carbide devices which pass an electrical test. The first contact of the identified ones of the silicon carbide devices are then selectively interconnected. Devices having a plurality of selectively connected silicon carbide devices of the same type are also provided.

摘要翻译： 通过在预定图案的碳化硅晶片的至少一部分上形成多个相同类型的碳化硅器件来制造碳化硅器件。 碳化硅器件在碳化硅晶片的第一面上具有对应的第一接触。 多个碳化硅器件被电学测试以识别通过电测试的多个碳化硅器件中的一个。 所识别的碳化硅器件的第一接触然后被选择性地互连。 还提供了具有相同类型的多个选择性连接的碳化硅器件的器件。

公开(公告)号：US5972801A

公开(公告)日：1999-10-26

申请号：US554319

申请日：1995-11-08

申请人： Lori A. Lipkin ,  David B. Slater, Jr. ,  John W. Palmour

发明人： Lori A. Lipkin ,  David B. Slater, Jr. ,  John W. Palmour

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L21/316 ,  H01L31/0312 ,  H01L21/20

CPC分类号： H01L21/049 ,  Y10S438/931

摘要： A method is disclosed for obtaining improved oxide layers and resulting improved performance from oxide based devices. The method comprises exposing an oxide layer on a silicon carbide layer to an oxidizing source gas at a temperature below the temperature at which SiC would begin to oxidize at a significant rate, while high enough to enable the oxidizing source gas to diffuse into the oxide layer, and while avoiding any substantial additional oxidation of the silicon carbide, and for a time sufficient to densify the oxide layer and improve the interface between the oxide layer and the silicon carbide layer.

摘要翻译： 公开了一种用于获得改进的氧化物层的方法，并且由氧化物基器件导致改进的性能。 该方法包括将碳化硅层上的氧化物层暴露于氧化源气体中，该温度低于SiC以显着的速率开始氧化的温度，同时高到足以使氧化源气体扩散到氧化物层 并且同时避免碳化硅的任何实质的附加氧化，并且足以使氧化物层致密化并改善氧化物层和碳化硅层之间的界面的时间。

公开(公告)号：US5323022A

公开(公告)日：1994-06-21

申请号：US943043

申请日：1992-09-10

申请人： Robert C. Glass ,  John W. Palmour ,  Robert F. Davis ,  Lisa S. Porter

发明人： Robert C. Glass ,  John W. Palmour ,  Robert F. Davis ,  Lisa S. Porter

IPC分类号： H01L29/43 ,  H01L21/04 ,  H01L21/28 ,  H01L29/24 ,  H01L29/45 ,  H01L29/40 ,  H01L29/46 ,  H01L29/62

CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/45 ,  Y10S148/148

摘要： A method and resulting ohmic contact structure between a high work function metal and a wide bandgap semiconductor for which the work function of the metal would ordinarily be insufficient to form an ohmic contact between the metal and the semiconductor. The structure can withstand annealing while retaining ohmic characteristics. The ohmic contact structure comprises a portion of single crystal wide bandgap semiconductor material; a contact formed of a high work function metal on the semiconductor portion; and a layer of doped p-type semiconductor material between the single crystal portion and the metal contact. The doped layer has a sufficient concentration of p-type dopant to provide ohmic behavior between the metal and the semiconductor material.

摘要翻译： 高功函数金属和宽带隙半导体之间的方法和结果欧姆接触结构，金属的功函数通常不足以在金属和半导体之间形成欧姆接触。 该结构可以承受退火同时保持欧姆特性。 欧姆接触结构包括单晶宽带隙半导体材料的一部分; 在半导体部分上由高功函数金属形成的触点; 以及在单晶部分和金属接触之间的掺杂p型半导体材料层。 掺杂层具有足够的p型掺杂剂浓度以在金属和半导体材料之间提供欧姆特性。

公开(公告)号：US07135359B2

公开(公告)日：2006-11-14

申请号：US10845913

申请日：2004-05-14

申请人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

发明人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

IPC分类号： H01L21/332

CPC分类号： H01L31/1113 ,  Y10S438/931

摘要： Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

摘要翻译： 提供仅具有两个端子的大面积碳化硅器件，例如光激活碳化硅晶闸管。 碳化硅器件通过连接板选择性地并联连接。 还提供了碳化硅晶闸管，其具有暴露的碳化硅晶闸管的栅极区域的一部分，以允许大于约3.25eV的能量的光来激活晶闸管的栅极。 碳化硅晶闸管可以是对称的或不对称的。 多个碳化硅晶闸管可以形成在晶片，晶片的一部分或多个晶片上。 可以确定坏细胞，并且通过连接板选择性地连接良好的细胞。

公开(公告)号：US07067361B2

公开(公告)日：2006-06-27

申请号：US10706641

申请日：2003-11-12

申请人： Scott T. Allen ,  John W. Palmour ,  Terrence S. Alcorn

发明人： Scott T. Allen ,  John W. Palmour ,  Terrence S. Alcorn

IPC分类号： H01L21/338

CPC分类号： H01L29/8128 ,  H01L21/7605 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/66068 ,  H01L29/66856 ,  H01L29/812

摘要： SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs. Also, source and drain ohmic contacts may be formed directly on the n-type channel layer, thus, the n+ regions need not be fabricated and the steps associated with such fabrication may be eliminated from the fabrication process. Methods of fabricating such SiC MESFETs and gate structures for SiC FETs as well as passivation layers are also disclosed.

摘要翻译： 公开了利用基本上不含深层掺杂剂的半绝缘SiC衬底的SiC MESFET。 半绝缘衬底的利用可能会降低MESFET的反向栅极效应。 还提供了具有两个凹陷栅极结构的SiC MESFET。 还提供了具有选择性掺杂的p型缓冲层的MESFET。 使用这种缓冲层可以将输出电导降低3倍，并且与传统的p型缓冲层相比，产生比SiC MESFET增加3db的功率增益。 还可以向p型缓冲层提供接地触点，并且p型缓冲层可以由两层p型层制成，其中在衬底上形成的层具有较高的掺杂剂浓度。 根据本发明实施例的SiC MESFET也可以使用铬作为肖特基栅极材料。 此外，可以利用氧化物 - 氮化物 - 氧化物（ONO）钝化层来降低SiC MESFET中的表面效应。 此外，源极和漏极欧姆接触可以直接形成在n型沟道层上，因此，不需要制造n +区域，并且可以从制造过程中消除与这种制造相关的步骤 。 还公开了制造这种SiC MESFET和用于SiC FET以及钝化层的栅极结构的方法。