公开(公告)号：US07915724B2

公开(公告)日：2011-03-29

申请号：US11864826

申请日：2007-09-28

申请人： Jong-Woo Ha ,  Koo Hong Lee ,  Soo Won Lee ,  JuHyun Park ,  Zigmund Ramirez Camacho ,  Jeffrey D. Punzalan ,  Lionel Chien Hui Tay ,  Jairus Legaspi Pisigan

发明人： Jong-Woo Ha ,  Koo Hong Lee ,  Soo Won Lee ,  JuHyun Park ,  Zigmund Ramirez Camacho ,  Jeffrey D. Punzalan ,  Lionel Chien Hui Tay ,  Jairus Legaspi Pisigan

IPC分类号： H01L23/02 ,  H01L23/42

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device.

摘要翻译： 一种集成电路封装系统，包括：形成具有开口的基座结构; 将基座结构装置安装在开口中; 将集成电路装置连接在所述基座结构装置上; 以及在所述基座结构，所述基座结构装置和所述集成电路装置上模制密封剂。

公开(公告)号：US20090085178A1

公开(公告)日：2009-04-02

申请号：US11864826

申请日：2007-09-28

申请人： Jong-Woo Ha ,  Koo Hong Lee ,  Soo Won Lee ,  JuHyun Park ,  Zigmund Ramirez Camacho ,  Jeffrey D. Punzalan ,  Lionel Chien Hui Tay ,  Jairus Legaspi Pisigan

发明人： Jong-Woo Ha ,  Koo Hong Lee ,  Soo Won Lee ,  JuHyun Park ,  Zigmund Ramirez Camacho ,  Jeffrey D. Punzalan ,  Lionel Chien Hui Tay ,  Jairus Legaspi Pisigan

IPC分类号： H01L23/495 ,  H01L23/02

CPC分类号： H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device.

摘要翻译： 一种集成电路封装系统，包括：形成具有开口的基座结构; 将基座结构装置安装在开口中; 将集成电路装置连接在所述基座结构装置上; 以及在所述基座结构，所述基座结构装置和所述集成电路装置上模制密封剂。

公开(公告)号：US08710675B2

公开(公告)日：2014-04-29

申请号：US11677477

申请日：2007-02-21

申请人： Young Cheol Kim ,  Koo Hong Lee

发明人： Young Cheol Kim ,  Koo Hong Lee

IPC分类号： H01L23/48 ,  H01L29/40 ,  H01L23/52 ,  H01L21/44

CPC分类号： H01L23/3107 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An integrated circuit package system includes a first integrated circuit die having die pads only adjacent a single edge of the first integrated circuit die, forming first bonding lands adjacent the single edge, connecting the die pads and the first bonding lands, and encapsulating the die pads and a portion of the first bonding lands to form a first package.

摘要翻译： 集成电路封装系统包括第一集成电路管芯，其具有仅与第一集成电路管芯的单个边缘相邻的管芯焊盘，形成与单个边缘相邻的第一焊接区域，连接管芯焊盘和第一焊接区域，以及封装管芯焊盘 并且所述第一结合区域的一部分形成第一包装。

公开(公告)号：US20110215456A1

公开(公告)日：2011-09-08

申请号：US13112717

申请日：2011-05-20

申请人： Youngcheol Kim ,  Myung Kil Lee ,  Gwang Kim ,  Koo Hong Lee

发明人： Youngcheol Kim ,  Myung Kil Lee ,  Gwang Kim ,  Koo Hong Lee

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant.

摘要翻译： 具有外部端子的薄封装系统的制造方法包括：提供引线框架; 提供用于定义外部粘结手指的模板; 在引线框架上的模板中形成外部粘结指状物; 通过第一多层电镀形成焊盘端子; 提供一个模具; 使用引线框上的粘合剂将管芯附接到引线框架上方的焊盘端子; 覆盖在所述管芯和所述外部粘结指状物的至少部分上的密封剂; 并且移除引线框架，使粘合剂的表面与密封剂的表面共面。

公开(公告)号：US08012867B2

公开(公告)日：2011-09-06

申请号：US11618647

申请日：2006-12-29

申请人： Koo Hong Lee ,  Il Kwon Shim ,  Young Cheol Kim ,  Bongsuk Choi

发明人： Koo Hong Lee ,  Il Kwon Shim ,  Young Cheol Kim ,  Bongsuk Choi

IPC分类号： H01L21/44

CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.

摘要翻译： 提供晶片级芯片级封装系统，包括将第一集成电路放置在具有第二集成电路的半导体晶片上; 连接第一集成电路和第二集成电路之间的第二电互连; 在所述第二集成电路的外周上形成用于覆盖所述第二电互连的应力消除密封剂; 以及从半导体晶片，通过应力释放密封剂和半导体晶片分离芯片级封装。

公开(公告)号：US20070178667A1

公开(公告)日：2007-08-02

申请号：US11618647

申请日：2006-12-29

申请人： Koo Hong Lee ,  Il Kwon Shim ,  Young Cheol Kim ,  Bongsuk Choi

发明人： Koo Hong Lee ,  Il Kwon Shim ,  Young Cheol Kim ,  Bongsuk Choi

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.

摘要翻译： 提供晶片级芯片级封装系统，包括将第一集成电路放置在具有第二集成电路的半导体晶片上; 连接第一集成电路和第二集成电路之间的第二电互连; 在所述第二集成电路的外周上形成用于覆盖所述第二电互连的应力消除密封剂; 以及从半导体晶片，通过应力释放密封剂和半导体晶片分离芯片级封装。

公开(公告)号：US08471374B2

公开(公告)日：2013-06-25

申请号：US11677487

申请日：2007-02-21

申请人： Young Cheol Kim ,  Koo Hong Lee ,  Jae Hak Yee

发明人： Young Cheol Kim ,  Koo Hong Lee ,  Jae Hak Yee

IPC分类号： H01L23/3121 ,  H01L24/49 ,  H01L25/0657

CPC分类号： H01L23/3107 ,  H01L21/6835 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system includes a first integrated circuit die having die pads only adjacent a single edge of the first integrated circuit die, forming first L-shaped leadfingers adjacent the single edge, connecting the die pads and the first L-shaped leadfingers, and encapsulating the die pads and portions of the first L-shaped leadfingers to form a first package.

摘要翻译： 集成电路封装系统包括具有与第一集成电路管芯的单个边缘相邻的管芯焊盘的第一集成电路管芯，与单个边缘相邻形成第一L形引线管，连接管芯焊盘和第一L形引线管，以及 封装所述管芯焊盘和所述第一L形引线管的部分以形成第一封装。

公开(公告)号：US08067272B2

公开(公告)日：2011-11-29

申请号：US12578797

申请日：2009-10-14

申请人： Young Cheol Kim ,  Koo Hong Lee ,  Jae Hak Yee ,  Ii Kwon Shim

发明人： Young Cheol Kim ,  Koo Hong Lee ,  Jae Hak Yee ,  Ii Kwon Shim

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/495

CPC分类号： H01L23/49537 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second integrated circuit die and the base, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.

摘要翻译： 提供了一种可堆叠的多芯片封装系统，包括形成具有基极和尖端的外部互连件，连接第一集成电路管芯和基座，将第二集成电路管芯在有源侧的第一集成电路管芯上堆叠到有源侧 配置，连接第二集成电路管芯和基座，以及模制第一集成电路管芯，第二集成电路管芯和部分暴露的外部互连。

公开(公告)号：US20100038768A1

公开(公告)日：2010-02-18

申请号：US12578797

申请日：2009-10-14

申请人： Young Cheol Kim ,  Koo Hong Lee ,  Jae Hak Yee ,  Il Kwon Shim

发明人： Young Cheol Kim ,  Koo Hong Lee ,  Jae Hak Yee ,  Il Kwon Shim

IPC分类号： H01L25/065 ,  H01L21/50

CPC分类号： H01L23/49537 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stackable multi-chip package system is provided including forming an external interconnect having a base and a tip, connecting a first integrated circuit die and the base, stacking a second integrated circuit die over the first integrated circuit die in an active side to active side configuration, connecting the second integrated circuit die and the base, and molding the first integrated circuit die, the second integrated circuit die, and the external interconnect partially exposed.

摘要翻译： 提供了一种可堆叠的多芯片封装系统，包括形成具有基极和尖端的外部互连件，连接第一集成电路管芯和基座，将第二集成电路管芯在有源侧的第一集成电路管芯上堆叠到有源侧 配置，连接第二集成电路管芯和基座，以及模制第一集成电路管芯，第二集成电路管芯和部分暴露的外部互连。

公开(公告)号：US07521297B2

公开(公告)日：2009-04-21

申请号：US11276948

申请日：2006-03-17

申请人： SeongMin Lee ,  SeungYun Ahn ,  Koo Hong Lee

发明人： SeongMin Lee ,  SeungYun Ahn ,  Koo Hong Lee

IPC分类号： H01L21/00

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multichip package system is provided forming a substrate having a plurality of molding transfer channel, connecting a first integrated circuit die on a top side of the substrate, connecting a second integrated circuit die on a bottom side of the substrate, and concurrently encapsulating the first integrated circuit die and the second integrated circuit die with a molding compound flow through the plurality of the molding transfer channels.

摘要翻译： 提供了一种多芯片封装系统，其形成具有多个成型传送沟道的基板，将基板的顶侧上的第一集成电路管芯连接，在基板的底侧连接第二集成电路管芯，并且同时封装第一 集成电路管芯和具有模制复合物的第二集成电路管芯流过多个模制传输通道。