公开(公告)号：US08513802B2

公开(公告)日：2013-08-20

申请号：US13013290

申请日：2011-01-25

申请人： Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-Il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

发明人： Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-Il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555

摘要： A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.

摘要翻译： 提供具有不同厚度的半导体芯片的半导体器件。 半导体器件可以包括第一半导体芯片，在第一半导体芯片的第一侧上的子板，在第一半导体芯片的第二侧上的至少一个第二半导体芯片，至少一个外部接触端子 一秒钟的半导体芯片。 在示例实施例中，所述至少一个第二半导体芯片可以包括多个通孔硅通孔，并且所述至少一个外部接触端子可以经由多个通孔与第一半导体芯片和至少一个第二半导体芯片电接触 通孔 在示例实施例中，至少一个第二半导体芯片可以比第一半导体芯片更薄。

公开(公告)号：US20110193229A1

公开(公告)日：2011-08-11

申请号：US13013290

申请日：2011-01-25

申请人： Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

发明人： Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555

摘要： A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.

摘要翻译： 提供具有不同厚度的半导体芯片的半导体器件。 半导体器件可以包括第一半导体芯片，在第一半导体芯片的第一侧上的子板，在第一半导体芯片的第二侧上的至少一个第二半导体芯片，至少一个外部接触端子 一秒钟的半导体芯片。 在示例实施例中，所述至少一个第二半导体芯片可以包括多个通孔硅通孔，并且所述至少一个外部接触端子可以经由多个通孔与第一半导体芯片和至少一个第二半导体芯片电接触 通孔 在示例实施例中，至少一个第二半导体芯片可以比第一半导体芯片更薄。

公开(公告)号：US08183673B2

公开(公告)日：2012-05-22

申请号：US12565969

申请日：2009-09-24

申请人： Son-Kwan Hwang ,  Keum-Hee Ma ,  Seung-Woo Shin ,  Min-Seung Yoon ,  Jong-Ho Yun ,  Ui-Hyoung Lee

发明人： Son-Kwan Hwang ,  Keum-Hee Ma ,  Seung-Woo Shin ,  Min-Seung Yoon ,  Jong-Ho Yun ,  Ui-Hyoung Lee

IPC分类号： H01L23/495

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2224/05552

摘要： A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via. Related methods of fabrication are also discussed.

摘要翻译： 如本文提供的微电子器件结构包括导电通孔，其导体通孔具有从其上表面延伸到衬底中的主体部分和沿衬底的上表面横向延伸的连接部分。 连接部分包括与衬底的上表面相对的凹部。 凹槽被限制在导电通孔的连接部分内，并且不延伸到衬底的上表面之下。 还提供了一种微电子器件结构，其包括导电通孔，该导电通孔具有从其上表面延伸到衬底中的主体部分和位于衬底的上表面下方的端部。 端部具有比主体部分宽的宽度。 在端部设置焊料可湿性层。 焊料可湿性层由导电金属具有比导电通孔的端部润湿性更高的润湿性的材料形成。 还讨论了相关的制造方法。

公开(公告)号：US20100096753A1

公开(公告)日：2010-04-22

申请号：US12565969

申请日：2009-09-24

申请人： Son-Kwan Hwang ,  Keum-Hee Ma ,  Seung-Woo Shin ,  Min-Seung Yoon ,  Jong-Ho Yun ,  Ui-Hyoung Lee

发明人： Son-Kwan Hwang ,  Keum-Hee Ma ,  Seung-Woo Shin ,  Min-Seung Yoon ,  Jong-Ho Yun ,  Ui-Hyoung Lee

IPC分类号： H01L23/498 ,  H01L21/98

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2224/05552

摘要： A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via. Related methods of fabrication are also discussed.

摘要翻译： 如本文提供的微电子器件结构包括导电通孔，其导体通孔具有从其上表面延伸到衬底中的主体部分和沿衬底的上表面横向延伸的连接部分。 连接部分包括与衬底的上表面相对的凹部。 凹槽被限制在导电通孔的连接部分内，并且不延伸到衬底的上表面之下。 还提供了一种微电子器件结构，其包括导电通孔，该导电通孔具有从其上表面延伸到衬底中的主体部分和位于衬底的上表面下方的端部。 端部具有比主体部分宽的宽度。 在端部设置焊料可湿性层。 焊料可湿性层由导电金属具有比导电通孔的端部润湿性更高的润湿性的材料形成。 还讨论了相关的制造方法。

公开(公告)号：US20110097891A1

公开(公告)日：2011-04-28

申请号：US12906578

申请日：2010-10-18

申请人： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

发明人： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Il Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.

摘要翻译： 制造半导体器件的方法包括制备具有与第一表面相对的第一表面和第二表面的衬底。 在第二表面上形成第一绝缘层。 牺牲层形成在第一绝缘层上。 形成开口以穿透基底并从第一表面延伸到牺牲层的一部分。 第二绝缘层形成在开口的内壁上。 形成塞子以填充开口。 去除牺牲层以通过第二表面暴露插塞的下部。

公开(公告)号：US08114772B2

公开(公告)日：2012-02-14

申请号：US12906578

申请日：2010-10-18

申请人： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Ii Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

发明人： Kyu-Ha Lee ,  Min-Seung Yoon ,  Ui-Hyoung Lee ,  Ju-Ii Choi ,  Nam-Seog Kim ,  Keum-Hee Ma

IPC分类号： H01L21/44

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface.

摘要翻译： 制造半导体器件的方法包括制备具有与第一表面相对的第一表面和第二表面的衬底。 在第二表面上形成第一绝缘层。 牺牲层形成在第一绝缘层上。 形成开口以穿透基底并从第一表面延伸到牺牲层的一部分。 第二绝缘层形成在开口的内壁上。 形成塞子以填充开口。 去除牺牲层以通过第二表面暴露插塞的下部。

公开(公告)号：US07777323B2

公开(公告)日：2010-08-17

申请号：US11750663

申请日：2007-05-18

申请人： Yong Chai Kwon ,  Keum-Hee Ma ,  Kang-Wook Lee ,  Dong-Ho Lee ,  Seong-il Han

发明人： Yong Chai Kwon ,  Keum-Hee Ma ,  Kang-Wook Lee ,  Dong-Ho Lee ,  Seong-il Han

IPC分类号： H01L23/12 ,  H01L21/44

CPC分类号： H01L21/76898 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00

摘要： Example embodiments are directed to a method of forming a semiconductor structure and a semiconductor structure including a semiconductor unit including a protrusion on a front side of the semiconductor unit and a recess on a backside of the semiconductor unit.

摘要翻译： 示例性实施例涉及一种形成半导体结构的方法和包括半导体单元的半导体结构的方法，所述半导体单元包括在半导体单元的前侧上的突起和半导体单元的背侧上的凹部。

公开(公告)号：US20070007641A1

公开(公告)日：2007-01-11

申请号：US11348670

申请日：2006-02-06

申请人： Kang-Wook Lee ,  Gu-Sung Kim ,  Yong-Chai Kwon ,  Keum-Hee Ma ,  Seong-Il Han

发明人： Kang-Wook Lee ,  Gu-Sung Kim ,  Yong-Chai Kwon ,  Keum-Hee Ma ,  Seong-Il Han

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012

摘要： A method for fabricating a chip-embedded interposer may comprise forming at least one cavity on a silicon substrate, forming a plurality of through vias penetrating the silicon substrate, providing an integrated circuit chip having a plurality of I/O pads, and forming rerouting conductors connected to the I/O pads and the through vias. A stack structure having different kinds of chips may be incorporated at wafer level using the described interposer.

摘要翻译： 芯片嵌入式插入器的制造方法可以包括在硅衬底上形成至少一个空腔，形成穿过硅衬底的多个通孔，提供具有多个I / O焊盘的集成电路芯片，以及形成重新布线的导体 连接到I / O焊盘和通孔。 具有不同种类的芯片的堆叠结构可以使用所描述的插入器结合在晶片级。

公开(公告)号：US20080318363A1

公开(公告)日：2008-12-25

申请号：US12213857

申请日：2008-06-25

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

IPC分类号： H01L21/00

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68354 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29011 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

摘要： A stack circuit member may include a first circuit member and a second circuit member. The first and the second circuit members may be electrically and mechanically connected together using a thermocompression bonding method. A photosensitive polymer layer may be interposed between the first circuit member and the second circuit member. A gap fill process and an electrical connection process may be performed at the same time.

摘要翻译： 堆叠电路构件可以包括第一电路构件和第二电路构件。 第一和第二电路构件可以使用热压接法将电气和机械连接在一起。 感光性聚合物层可以设置在第一电路部件和第二电路部件之间。 间隙填充处理和电连接处理可​​以同时进行。

公开(公告)号：US07459774B2

公开(公告)日：2008-12-02

申请号：US11436851

申请日：2006-05-18

申请人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

发明人： Yong-Chai Kwon ,  Kang-Wook Lee ,  Keum-Hee Ma ,  Seong-II Han

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/31 ,  H01L24/83 ,  H01L24/90 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/08112 ,  H01L2224/13009 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/81141 ,  H01L2224/83136 ,  H01L2224/83194 ,  H01L2224/838 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552

摘要： In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with such voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips/wafers is greatly improved, while providing complete gap fill. In addition, mechanical reliability is improved, alleviating the problems associated with cracking and delamination, and leading to an improvement in device yield and device reliability.

摘要翻译： 在堆叠式芯片构造及其制造方法中，使用消除下部和上部切屑之间的空隙以及与这种空隙相关的裂纹和分层问题的相对简单的工艺，完全填充下部和上部切屑之间的间隙。 本发明可应用于芯片级接合和晶片级接合方式。 在堆叠芯片或堆叠晶片之前，将光敏聚合物层施加到第一芯片或晶片。 感光性聚合物层被部分固化，使得光敏聚合物层在结构上稳定，同时保持其粘合性能。 第二芯片或晶片被堆叠，对准并且结合到第一芯片或晶片，然后使光敏聚合物层固化以完全结合第一和​​第二芯片或晶片。 以这种方式，在提供完全的间隙填充的同时，大大提高了芯片/晶片之间的粘附。 此外，机械可靠性得到改善，减轻了与开裂和分层相关的问题，从而提高了设备​​的产量和设备的可靠性。