公开(公告)号：US06323518B1

公开(公告)日：2001-11-27

申请号：US09394047

申请日：1999-09-13

申请人： Kozo Sakamoto ,  Yoshito Nakazawa ,  Eiji Yanokura

发明人： Kozo Sakamoto ,  Yoshito Nakazawa ,  Eiji Yanokura

IPC分类号： H01L2362

CPC分类号： H01L29/7813 ,  H01L23/62 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7815 ,  H01L2924/0002 ,  H01L2924/00

摘要： Plural grooves are formed in a main surface of semiconductor layers on semiconductor substrate, and gate layers connected to a gate electrode are formed in the plural grooves through a gate insulating film, and then a body diffusion layer is formed between the gate layers, and afterwards, a source diffusion layer connected to a source electrode and a source diffusion layer connected to a source electrode are formed in an identical process.

摘要翻译： 在半导体衬底上的半导体层的主表面上形成有多个沟槽，并且通过栅极绝缘膜在多个沟槽中形成与栅电极连接的栅极层，然后在栅极层之间形成体扩散层，之后 以与该源电极连接的源极扩散层和与源电极连接的源极扩散层以相同的工序形成。

公开(公告)号：US08455943B2

公开(公告)日：2013-06-04

申请号：US13181816

申请日：2011-07-13

申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

IPC分类号： H01L29/66 ,  H01L29/40

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806

摘要： Provided is a technology, in a semiconductor device having a power MISFET and a Schottky barrier diode on one semiconductor substrate, capable of suppressing a drastic increase in the on-resistance of the power MISFET while making the avalanche breakdown voltage of the Schottky barrier diode greater than that of the power MISFET. In the present invention, two epitaxial layers, one having a high doping concentration and the other having a low doping concentration, are formed over a semiconductor substrate and the boundary between these two epitaxial layers is located in a region equal in depth to or shallower than the bottom portion of a trench.

摘要翻译： 提供了一种在一个半导体衬底上具有功率MISFET和肖特基势垒二极管的半导体器件中的技术，其能够抑制功率MISFET的导通电阻的急剧增加，同时使肖特基势垒二极管的雪崩击穿电压更大 比功率MISFET。 在本发明中，在半导体衬底上形成两个外延层，一个具有高掺杂浓度且另一个具有低掺杂浓度的外延层，并且这两个外延层之间的边界位于相同深度或更浅的区域 沟槽的底部。

公开(公告)号：US08354713B2

公开(公告)日：2013-01-15

申请号：US13107542

申请日：2011-05-13

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L29/66

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

公开(公告)号：US20110204413A1

公开(公告)日：2011-08-25

申请号：US13060737

申请日：2010-02-25

申请人： Daisuke Arai ,  Yoshito Nakazawa ,  Norio Hosoya

发明人： Daisuke Arai ,  Yoshito Nakazawa ,  Norio Hosoya

IPC分类号： H01L29/74 ,  H01L21/332

CPC分类号： H01L29/7395 ,  H01L24/05 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66333 ,  H01L2224/04042 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/00

摘要： In order to improve characteristics of an IGBT, particularly, to reduce steady loss, turn-off time and turn-off loss, a thickness of a surface semiconductor layer is set to about 20 nm to 100 nm in an IGBT including: a base layer; a buried insulating film provided with an opening part; the surface semiconductor layer connected to the base layer below the opening part; a p type channel forming layer formed in the surface semiconductor layer; an n+ type source layer; a p+ type emitter layer; a gate electrode formed over the surface semiconductor layer via a gate insulating film; an n+ type buffer layer; and a p type collector layer.

摘要翻译： 为了改善IGBT的特性，特别是为了减少稳定损耗，关断时间和关断损耗，在包括基底层的IGBT中，表面半导体层的厚度设定为约20nm至100nm ; 设置有开口部的埋入绝缘膜; 所述表面半导体层在所述开口部的下方与所述基底层连接; 形成在所述表面半导体层中的p型沟道形成层; n +型源层; p +型发射极层; 栅电极，经由栅极绝缘膜形成在所述表面半导体层上; n +型缓冲层; 和p型集电体层。

公开(公告)号：US07981747B2

公开(公告)日：2011-07-19

申请号：US12385979

申请日：2009-04-27

申请人： Masaki Shiraishi ,  Yoshito Nakazawa

发明人： Masaki Shiraishi ,  Yoshito Nakazawa

IPC分类号： H01L29/72

CPC分类号： H01L29/7811 ,  H01L21/26586 ,  H01L24/05 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2224/05552 ,  H01L2224/0603 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p−type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p−type semiconductor region is formed under a n+type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

摘要翻译： 提供了一种降低导通电阻的技术，并且相对于沟槽栅型功率MISFET实现了穿通的防止。 输入电容和反馈电容通过形成栅极形成的沟槽而减小，使得深度为约1μm以下的深度，将ap型半导体区形成为不覆盖的深度 并且在作为沟槽栅型功率MISFET的源极区域的n +型半导体区域之下形成杂质浓度高于p型半导体区域的p型半导体区域，使p型半导体区域 半导体区域用作沟槽栅型功率MISFET的穿通阻挡层。

公开(公告)号：US07834407B2

公开(公告)日：2010-11-16

申请号：US12471680

申请日：2009-05-26

申请人： Yoshito Nakazawa ,  Yuji Yatsuda

发明人： Yoshito Nakazawa ,  Yuji Yatsuda

IPC分类号： H01L27/088

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

摘要翻译： 在具有具有虚拟栅电极的沟槽栅极结构的功率MISFET中，提供了用于改善功率MISFET的性能的技术，同时防止其中的栅极绝缘膜的静电击穿。 在相同的半导体衬底上形成具有具有虚拟栅电极的沟槽栅极结构和保护二极管的功率MISFET。 保护二极管设置在源电极和栅极互连之间。 在这种半导体器件的制造方法中，同时形成用于伪栅电极的多晶硅膜和用于保护二极管的多晶硅膜。 在同一步骤中形成功率MISFET的源极区域和保护二极管的n +型半导体区域。

公开(公告)号：US07595242B2

公开(公告)日：2009-09-29

申请号：US11958363

申请日：2007-12-17

申请人： Yoshito Nakazawa ,  Hitoshi Matsuura

发明人： Yoshito Nakazawa ,  Hitoshi Matsuura

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

摘要翻译： 提供高性能的沟槽栅型功率晶体管。 作为栅电极的沟槽栅极形成为包括漏极层和外延层的超结结构。 在这种情况下，栅电极形成为使得外延层的上表面高于在漏极层上形成的沟道层的上表面。 然后，在沟道层和外延层的每一个上形成绝缘膜，然后去除绝缘膜的一部分，以在外延层的侧壁上形成侧壁间隔物。 随后，以侧壁间隔物作为掩模，去除沟道层的一部分和漏极层的一部分，以形成用于沟槽栅的沟槽。

公开(公告)号：US20080057650A1

公开(公告)日：2008-03-06

申请号：US11875707

申请日：2007-10-19

申请人： Tomoaki Uno ,  Yoshito Nakazawa

发明人： Tomoaki Uno ,  Yoshito Nakazawa

IPC分类号： H01L21/336

CPC分类号： H01L29/66727 ,  H01L23/50 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7839 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an n-channel type power MISFET, a source electrode in contact with an n+-semiconductor region (source region) and a p+-semiconductor region (back gate contact region) is constituted with an Al film and an underlying barrier film comprised of MoSi2, use of the material having higher barrier height relation to n-Si for the barrier film increasing the contact resistance to n-Si and backwardly biasing the emitter and base of a parasitic bipolar transistor making it less tending to turn-on, thereby decreasing the leak current of power MISFET.

摘要翻译： 在n沟道型功率MISFET中，与n + / - 半导体区域（源极区域）和ap + + - 半导体区域（背栅极接触区域 ）由Al膜和由MoSi 2 N构成的下面的阻挡膜构成，使用与n-Si相比具有更高的势垒高度的材料用于阻挡膜增加与n-Si的接触电阻，以及 向后偏置寄生双极晶体管的发射极和基极，使其不易于接通，从而减小功率MISFET的漏电流。

公开(公告)号：US20070290268A1

公开(公告)日：2007-12-20

申请号：US11889099

申请日：2007-08-09

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakae Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L29/76

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

公开(公告)号：US20070111423A1

公开(公告)日：2007-05-17

申请号：US11653418

申请日：2007-01-16

申请人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakee Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

发明人： Sumito Numazawa ,  Yoshito Nakazawa ,  Masayoshi Kobayashi ,  Satoshi Kudo ,  Yasuo Imai ,  Sakee Kubo ,  Takashi Shigematsu ,  Akihiro Ohnishi ,  Kozo Uesawa ,  Kentaro Oishi

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

摘要翻译： 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的深度方向上作为漏极区域的第一导电型半导体层的主表面形成沟槽，形成栅极 在沟槽的内表面上形成包括热氧化膜和沉积膜的绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成半导体区域 用作沟道形成区域的第二导电类型，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。