公开(公告)号：US5359561A

公开(公告)日：1994-10-25

申请号：US872958

申请日：1992-04-23

申请人： Shigetoshi Sakomura ,  Kazuya Ito ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Tomoshi Matsumoto, deceased

发明人： Shigetoshi Sakomura ,  Kazuya Ito ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara ,  Tomoshi Matsumoto, deceased

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  G11C7/00

CPC分类号： G11C29/24

摘要： A semiconductor memory device is provided which includes a plurality of data lines, at least one redundant data line, one common data line, a plurality of column switches installed between the plurality of data lines and the redundant data line and one common data line, and a column decoder for controlling the plurality of column switches. The column decoder operates to turn the column switch on. The column switch is connected to a plurality of data lines, excluding any defective data and redundant data lines during the test mode state.

摘要翻译： 提供一种半导体存储器件，其包括多个数据线，至少一个冗余数据线，一个公共数据线，安装在多个数据线与冗余数据线和一条公共数据线之间的多个列开关，以及 用于控制多个列开关的列解码器。 列解码器操作以打开列开关。 列开关连接到多个数据线，在测试模式状态期间不包括任何有缺陷的数据和冗余数据线。

公开(公告)号：US5410507A

公开(公告)日：1995-04-25

申请号：US977212

申请日：1992-11-16

申请人： Masanori Tazunoki ,  Shigetoshi Sakomura ,  Toshitsugu Takekuma ,  Yutaka Ito ,  Kazuya Ito ,  Wataru Arakawa ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara

发明人： Masanori Tazunoki ,  Shigetoshi Sakomura ,  Toshitsugu Takekuma ,  Yutaka Ito ,  Kazuya Ito ,  Wataru Arakawa ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Masamichi Ishihara

IPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C13/00

CPC分类号： G11C11/4076 ,  G11C11/4074

摘要： A dynamic RAM provided with a data retention mode intended for low power consumption is provided. In the data retention mode, the current supply capabilities of voltage generation circuits which generate decreased voltage, increased voltage, reference voltage, etc., are limited in the range in which information retention operation in memory cells can be maintained, and the number of selected memory mats in the data retention mode is increased with respect to that of memory mats selected in the normal read/write mode and refresh mode. Special modes such as the data retention mode are set by combining an address strobe signal and other control signals and dummy CBR refresh is executed to release the special mode.

摘要翻译： 提供了具有旨在低功耗的数据保留模式的动态RAM。 在数据保持模式下，产生电压降低，电压升高，参考电压等的电压产生电路的电流供应能力在保持存储器单元的信息保持操作的范围内被限制，并且所选择的数量 相对于在正常读/写模式和刷新模式中选择的存储器垫，数据保持模式中的存储器垫增加。 通过组合地址选通信号和其他控制信号来设置数据保持模式等特殊模式，执行虚拟CBR刷新以释放特殊模式。

公开(公告)号：US5217917A

公开(公告)日：1993-06-08

申请号：US496280

申请日：1990-03-20

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takemuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5426613A

公开(公告)日：1995-06-20

申请号：US972907

申请日：1992-11-06

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

摘要翻译： 提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。 结合这些，接合垫被布置在适于不同包装类型的最佳位置处。 还提供了各种布局布置以最小化空间并改善访问时间。 提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

公开(公告)号：US5805513A

公开(公告)日：1998-09-08

申请号：US432867

申请日：1995-05-02

申请人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

发明人： Yasushi Takahashi ,  Hidetoshi Iwai ,  Satoshi Oguchi ,  Hisashi Nakamura ,  Hiroyuki Uchiyama ,  Toshitugu Takekuma ,  Shigetoshi Sakomura ,  Kazuyuki Miyazawa ,  Masamichi Ishihara ,  Ryoichi Hori ,  Takeshi Kizaki ,  Yoshihisa Koyama ,  Haruo Ii ,  Masaya Muranaka ,  Hidetomo Aoyagi ,  Hiromi Matsuura

IPC分类号： G11C5/00 ,  G11C5/02 ,  G11C7/10 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/027 ,  G11C11/4074 ,  G11C11/4082 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/00 ,  G11C5/025 ,  G11C7/1045 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/78

摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.

公开(公告)号：US5208782A

公开(公告)日：1993-05-04

申请号：US892708

申请日：1992-05-29

申请人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

发明人： Toshiyuki Sakuta ,  Masamichi Ishihara ,  Kazuyuki Miyazawa ,  Masanori Tazunoki ,  Hidetoshi Iwai ,  Hisashi Nakamura ,  Yasushi Takahashi ,  Toshio Maeda ,  Hiromi Matsuura ,  Ryoichi Hori ,  Toshio Sasaki ,  Osamu Sakai ,  Hiroyuki Uchiyama ,  Eiji Miyamoto ,  Kazuyoshi Oshima ,  Yasuhiro Kasama

IPC分类号： G06F11/18 ,  G06F11/20 ,  G11C11/406 ,  G11C29/00 ,  H01L27/105 ,  H01L27/108

CPC分类号： G11C29/808 ,  G11C11/406 ,  G11C29/88 ,  H01L24/06 ,  H01L27/10805 ,  G06F11/1666 ,  G06F11/183 ,  H01L2224/4826 ,  H01L27/105 ,  H01L2924/13091 ,  H01L2924/14

摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.

摘要翻译： 提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。 为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。 在芯片上提供了多个宏单元存储块通用的其他外围电路。 宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。 宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。 这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

公开(公告)号：US5289416A

公开(公告)日：1994-02-22

申请号：US820489

申请日：1992-01-14

申请人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

发明人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

IPC分类号： G11C11/401 ,  G06F11/20 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： H01L21/76894 ,  G11C29/83 ,  G11C29/832 ,  H01L21/76888 ,  G11C8/16

摘要： An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.

摘要翻译： 提供一种用于在切换到冗余电路之后防止存储器或逻辑器件中的DC缺陷的布置，通过切断通过故障元件或电路的漏电流路径来提高器件的产品产量。 由该预定布线整体形成的切割点或其一部分设置在该装置上。 通过预定的测试设备在晶片状态下执行形成的芯片的探针测试，并且基于测试结果产生关于切割点的切割的布线校正数据。 此外，该布线校正数据以线上方式发送到布线校正设备，使得可以切割相应的切割点。 布线校正装置可以由EB直接书写装置，FIB装置或激光修复装置形成。 利用这种布置，切割由常规电路中未使用的缺陷元件或电路形成的漏电流路径，并且显着提高器件的产品产量。 这种布置可以用于各种存储器或逻辑器件，包括DRAM，SRAM，多端口存储器和门阵列。

公开(公告)号：US5483490A

公开(公告)日：1996-01-09

申请号：US159619

申请日：1993-12-01

申请人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

发明人： Hidetoshi Iwai ,  Masamichi Ishihara ,  Kazuya Ito ,  Wataru Arakawa ,  Yoshinobu Nakagome

IPC分类号： G11C11/401 ,  G06F11/20 ,  G11C11/409 ,  G11C29/00 ,  G11C29/04 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： H01L21/76894 ,  G11C29/83 ,  G11C29/832 ,  H01L21/76888 ,  G11C8/16

摘要： An arrangement is provided for preventing DC defects in a memory or logic device after switching to a redundant circuit, improving the product yield of the device by cutting a leakage current path through a defective element or circuit. The cutting points formed by the predetermined wirings as a whole or a part thereof are provided to the device. A probe test of the formed chip is executed under the wafer condition by predetermined test equipment, and wiring correction data regarding the cutting of the cutting points is generated based on the result of test. Moreover, this wiring correction data is transmitted in an on-line fashion to the wiring correction equipment so that the corresponding cutting points can be cut. The wiring correction equipment can be formed by an EB direct writing apparatus, an FIB apparatus or a laser repair apparatus. With this arrangement, the leakage current path formed by a defective element or circuit left unused in conventional circuits is cut, and the product yield of the device is raised significantly. This arrangement can be used for a variety of memory or logic devices, including DRAMs, SRAMs, multiport memories and gate arrays.

摘要翻译： 提供一种用于在切换到冗余电路之后防止存储器或逻辑器件中的DC缺陷的布置，通过切断通过故障元件或电路的漏电流路径来提高器件的产品产量。 由该预定布线整体形成的切割点或其一部分设置在该装置上。 通过预定的测试设备在晶片状态下执行形成的芯片的探针测试，并且基于测试结果产生关于切割点的切割的布线校正数据。 此外，该布线校正数据以线上方式发送到布线校正设备，使得可以切割相应的切割点。 布线校正装置可以由EB直接书写装置，FIB装置或激光修复装置形成。 利用这种布置，切割由常规电路中未使用的缺陷元件或电路形成的漏电流路径，并且显着提高器件的产品产量。 这种布置可以用于各种存储器或逻辑器件，包括DRAM，SRAM，多端口存储器和门阵列。

公开(公告)号：US5594279A

公开(公告)日：1997-01-14

申请号：US149876

申请日：1993-11-10

申请人： Yutaka Itou ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Takumi Nasu ,  Tomohiro Suzuki

发明人： Yutaka Itou ,  Hidetoshi Iwai ,  Toshiyuki Sakuta ,  Takumi Nasu ,  Tomohiro Suzuki

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/552 ,  H01L23/48

CPC分类号： H01L24/06 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/4826 ,  H01L2224/48464 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025

摘要： A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8. Since the coupling impedance between shield wiring 1 and substrate 7 (due almost solely to the electrostatic capacitance Css) is large, and coupling impedance between Vss wiring 2 and substrate 7 (due almost solely to the junction capacitance D) is low, the noise caused by variations in the potential of substrate 7 is transferred to shield wiring 1, while it is not appreciably transferred to Vss wiring 2.

摘要翻译： 一种半导体器件，其中屏蔽布线布置在半导体衬底和用于提供电源电位或接地电位的电源布线之间。 基本上防止了由半导体衬底的电位变化所表示的噪声通过屏蔽布线转移到上述电源布线。 在一个方面，屏蔽布线1布置在用于向半导体衬底和衬底7上的各种电路供电的Vss布线之间。该屏蔽布线1经由M1片内布线4，M2片内连接到接地引线框架18 布线5，连接部40，接合焊盘3和接合线8.由于屏蔽布线1和基板7之间的耦合阻抗（几乎完全相当于静电电容Css），所以Vss布线2和基板7 由于几乎完全由结电容D）导致的，基板7的电位的变化引起的噪声被传送到屏蔽布线1，而不明显地转移到Vss布线2。

公开(公告)号：US5458998A

公开(公告)日：1995-10-17

申请号：US886403

申请日：1992-05-21

申请人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

发明人： Toshitsugu Takekuma ,  Toshio Suzuki ,  Hidetoshi Iwai ,  Masamichi Ishihara

IPC分类号： G03F1/00 ,  G03F1/26 ,  G03F1/30 ,  G03F1/36 ,  G03F1/68 ,  G03F1/84 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

CPC分类号： G03F1/26 ,  G03F1/29 ,  G03F1/84

摘要： Pattern data of a phase shift mask can be inspected: (101) by separating and laying out pattern data of a phase shift mask in an actual pattern data layer, an auxiliary pattern data layer and a phase shift pattern data layer; (102) by inspecting and correcting only the data of the actual pattern of the actual pattern data layer; (108) by making data of an estimated pattern estimated to be transferred to a semiconductor wafer from the data of the synthetic data of the correct actual pattern data, the auxiliary pattern data and the phase shift pattern data, which are inspected and corrected; and (104) by comparing the estimated pattern data and the actual pattern data to inspect the data of the auxiliary pattern and the phase shift pattern.

摘要翻译： 可以检查相移掩模的图案数据：（101）通过在实际图案数据层，辅助图案数据层和相移图案数据层中分离和布置相移掩模的图案数据; （102），通过检查和校正实际图案数据层的实际图案的数据; （108）通过从被检查和校正的正确的实际图案数据，辅助图案数据和相移图案数据的合成数据的数据中制作估计传送到半导体晶片的估计图案的数据; 和（104）通过比较估计的图案数据和实际图案数据来检查辅助图案和相移图案的数据。