利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

9 条记录 (耗时 0.047 秒)

    Method to avoid copper contamination on the sidewall of a via or a dual damascene structure
    5.
    发明授权
    Method to avoid copper contamination on the sidewall of a via or a dual damascene structure 有权
    避免在通孔或双镶嵌结构的侧壁上铜污染的方法

    公开(公告)号：US6114243A

    公开(公告)日：2000-09-05

    申请号：US439361

    申请日：1999-11-15

    申请人： Subhash Gupta ,  Kwok Keung Paul Ho ,  Mei-Sheng Zhou ,  Simon Chool

    发明人： Subhash Gupta ,  Kwok Keung Paul Ho ,  Mei-Sheng Zhou ,  Simon Chool

    IPC分类号： H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76877

    摘要： A new method to prevent copper contamination of the intermetal dielectric layer during via or dual damascene etching by forming a capping layer over the first copper metallization is described. A first copper metallization is formed in a dielectric layer overlying a semiconductor substrate wherein a barrier metal layer is formed underlying the first copper metallization and overlying the dielectric layer. The first copper metallization is planarized, then etched to form a recess below the surface of the dielectric layer. A conductive capping layer is deposited overlying the first copper metallization within the recess and overlying the dielectric layer. The conductive capping layer is removed except over the first copper metallization within the recess using one of several methods. An intermetal dielectric layer is deposited overlying the dielectric layer and the conductive capping layer overlying the first copper metallization. A via or dual damascene opening is etched through the intermetal dielectric layer to the conductive capping layer wherein the conductive capping layer prevents copper contamination of the intermetal dielectric layer during etching. The via or dual damascene opening is filled with a metal layer to complete electrical connections in the fabrication of an integrated circuit device.

    摘要翻译： 描述了在通过或双镶嵌蚀刻期间通过在第一铜金属化上形成覆盖层来防止金属间电介质层的铜污染的新方法。 第一铜金属化形成在覆盖半导体衬底的电介质层中，其中阻挡金属层形成在第一铜金属化层下方并且覆盖在电介质层上。 第一铜金属化被平坦化，然后被蚀刻以在介电层的表面下方形成凹陷。 导电覆盖层沉积在凹槽内的第一铜金属化层上并覆盖在介电层上。 使用几种方法之一除去在凹槽内的第一铜金属化之外除去导电覆盖层。 覆盖介电层和覆盖第一铜金属化的导电覆盖层的金属间电介质层被沉积。 通孔或双镶嵌开口通过金属间电介质层被蚀刻到导电覆盖层，其中导电覆盖层防止蚀刻期间金属间介电层的铜污染。 通孔或双镶嵌开口填充有金属层，以在集成电路器件的制造中完成电连接。

    Plasma etch method for forming plasma etched silicon layer
    7.
    发明授权
    Plasma etch method for forming plasma etched silicon layer 失效
    用于形成等离子体蚀刻硅层的等离子体蚀刻方法

    公开(公告)号：US06877517B2

    公开(公告)日：2005-04-12

    申请号：US10694413

    申请日：2003-10-27

    申请人： Kwok Keung Paul Ho ,  Xue Chun Dai

    发明人： Kwok Keung Paul Ho ,  Xue Chun Dai

    IPC分类号： H01L21/3065 ,  H01L21/302 ,  C23F5/00

    CPC分类号： H01J37/32495 ,  H01J37/32862 ,  H01J2237/022 ,  H01L21/3065 ,  Y10S438/905

    摘要： A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species. Within the plasma etch method: (1) a cleaned plasma reactor chamber is seasoned to provide a seasoned plasma reactor chamber having a seasoning polymer layer formed therein; (2) the first silicon layer is etched to form the etched first silicon layer within the seasoned plasma reactor chamber; and (3) the seasoning polymer layer is cleaned from the seasoned plasma reactor chamber to provide the cleaned plasma reactor chamber after etching the first silicon layer to form the etched first silicon layer within the seasoned plasma reactor chamber, prior to etching a second silicon layer to form an etched second silicon layer formed over a second substrate within the plasma reactor chamber while employing the plasma etch method in accord with (1), (2) and (3).

    摘要翻译： 一种形成蚀刻硅层的方法。 首先提供在第一硅层之上形成的第一衬底。 然后蚀刻第一硅层以形成蚀刻的第一硅层，同时采用等离子体蚀刻方法，其使用等离子体反应器室与等离子体蚀刻剂气体组合物结合，其在等离子体激活时提供至少一种含活性溴的蚀刻剂物质和 含活性氯的蚀刻剂物种。 在等离子体蚀刻方法中：（1）调节清洁的等离子体反应器室以提供其中形成有调味聚合物层的经验化的等离子体反应器室; （2）蚀刻第一硅层以在调味的等离子体反应器室内形成蚀刻的第一硅层; 和（3）从调味的等离子体反应器室中清洗调味聚合物层，以在刻蚀第一硅层之后提供经清洁的等离子体反应室，以在蚀刻第二硅层之前在调味的等离子体反应器室内形成蚀刻的第一硅层 以形成在等离子体反应器室内的第二衬底上形成的蚀刻的第二硅层，同时采用根据（1），（2）和（3）的等离子体蚀刻方法。

    Plasma etch method for forming plasma etched silicon layer
    8.
    发明授权
    Plasma etch method for forming plasma etched silicon layer 有权

    公开(公告)号：US06790374B1

    公开(公告)日：2004-09-14

    申请号：US09442499

    申请日：1999-11-18

    申请人： Kwok Keung Paul Ho ,  Xuechun Dai

    发明人： Kwok Keung Paul Ho ,  Xuechun Dai

    IPC分类号： H01L21302

    CPC分类号： H01J37/32495 ,  H01J37/32862 ,  H01J2237/022 ,  H01L21/3065 ,  Y10S438/905

    摘要： A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species. Within the plasma etch method: (1) a cleaned plasma reactor chamber is seasoned to provide a seasoned plasma reactor chamber having a seasoning polymer layer formed therein; (2) the first silicon layer is etched to form the etched first silicon layer within the seasoned plasma reactor chamber; and (3) the seasoning polymer layer is cleaned from the seasoned plasma reactor chamber to provide the cleaned plasma reactor chamber after etching the first silicon layer to form the etched first silicon layer within the seasoned plasma reactor chamber, prior to etching a second silicon layer to form an etched second silicon layer formed over a second substrate within the plasma reactor chamber while employing the plasma etch method in accord with (1), (2) and (3).

    Method and cleaner composition for stripping copper containing residue layers
    9.
    发明授权
    Method and cleaner composition for stripping copper containing residue layers 失效
    用于汽提含铜残渣层的方法和清洁剂组合物

    公开(公告)号：US06387859B1

    公开(公告)日：2002-05-14

    申请号：US09670327

    申请日：2000-09-27

    申请人： Kwok Keung Paul Ho

    发明人： Kwok Keung Paul Ho

    IPC分类号： C11D100

    CPC分类号： H01L21/02063 ,  C11D7/3218 ,  C11D11/0047 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H05K3/26

    摘要： A cleaner composition for removing from within a microelectronic fabrication a copper containing residue layer in the presence of a copper containing conductor layer, and a method for stripping from within a microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer. The cleaner composition comprises: (1) a hydroxyl amine material; (2) an ammonium fluoride material; and (3) a benzotriazole (BTA) material. The cleaner composition contemplates the method for stripping from within the microelectronic fabrication the copper containing residue layer in the presence of the copper containing conductor layer.

    摘要翻译： 一种清洁剂组合物，用于在含有铜的导体层的存在下从微电子制造中除去含铜残渣层，以及在含有铜的导体层存在下从微电子制造中剥离含铜残渣层的方法。 清洁剂组合物包括：（1）羟胺材料; （2）氟化铵材料; 和（3）苯并三唑（BTA）材料。 清洁剂组合物考虑了在含铜导体层存在下从微电子制造中剥离含铜残余层的方法。