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公开(公告)号：US20100221882A1
公开(公告)日：2010-09-02
申请号：US12662962
申请日：2010-05-13
IPC分类号： H01L21/336
CPC分类号： B82B1/005 , B82Y10/00 , H01L21/0237 , H01L21/02392 , H01L21/02521 , H01L21/02543 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L27/10808 , H01L27/10873 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/732 , H01L29/7371 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L33/02 , H01L33/18 , H01L33/20 , H01L33/24 , Y10S977/762 , Y10S977/938
摘要： The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
摘要翻译： 本发明涉及包含半导体纳米元件的半导体器件。 具体地说，本发明涉及一种具有体积元件的装置，该体积元件的直径大于与纳米元件外延连接的纳米元件的直径。 体积元件正在被掺杂以便提供高电荷载流子注入纳米元件和电连接中的低访问阻力。 纳米元件可以从半导体衬底直立。 在体积元件上形成的低电阻率材料的同心层形成接触。
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公开(公告)号：US20080149914A1
公开(公告)日：2008-06-26
申请号：US11812226
申请日：2007-06-15
CPC分类号： B82B1/005 , B82Y10/00 , H01L21/0237 , H01L21/02392 , H01L21/02521 , H01L21/02543 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L27/10808 , H01L27/10873 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/732 , H01L29/7371 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L33/02 , H01L33/18 , H01L33/20 , H01L33/24 , Y10S977/762 , Y10S977/938
摘要： The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
摘要翻译： 本发明涉及包含半导体纳米元件的半导体器件。 具体地说，本发明涉及一种具有体积元件的装置，该体积元件的直径大于与纳米元件外延连接的纳米元件的直径。 体积元件正在被掺杂以便提供高电荷载流子注入纳米元件和电连接中的低访问阻力。 纳米元件可以从半导体衬底直立。 在体积元件上形成的低电阻率材料的同心层形成接触。
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公开(公告)号：US08455857B2
公开(公告)日：2013-06-04
申请号：US13227950
申请日：2011-09-08
CPC分类号： B82B1/005 , B82Y10/00 , H01L21/0237 , H01L21/02392 , H01L21/02521 , H01L21/02543 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L27/10808 , H01L27/10873 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/732 , H01L29/7371 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L33/02 , H01L33/18 , H01L33/20 , H01L33/24 , Y10S977/762 , Y10S977/938
摘要： The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
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公开(公告)号：US08067299B2
公开(公告)日：2011-11-29
申请号：US12662962
申请日：2010-05-13
IPC分类号： H01L21/20 , H01L21/36 , H01L21/336
CPC分类号： B82B1/005 , B82Y10/00 , H01L21/0237 , H01L21/02392 , H01L21/02521 , H01L21/02543 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L27/10808 , H01L27/10873 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/732 , H01L29/7371 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L33/02 , H01L33/18 , H01L33/20 , H01L33/24 , Y10S977/762 , Y10S977/938
摘要： The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
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公开(公告)号：US08049203B2
公开(公告)日：2011-11-01
申请号：US11812226
申请日：2007-06-15
IPC分类号： H01L29/06
CPC分类号： B82B1/005 , B82Y10/00 , H01L21/0237 , H01L21/02392 , H01L21/02521 , H01L21/02543 , H01L21/02546 , H01L21/02603 , H01L21/02639 , H01L21/02645 , H01L21/02653 , H01L27/10808 , H01L27/10873 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L29/0676 , H01L29/732 , H01L29/7371 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L33/02 , H01L33/18 , H01L33/20 , H01L33/24 , Y10S977/762 , Y10S977/938
摘要： The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
摘要翻译： 本发明涉及包含半导体纳米元件的半导体器件。 具体地说，本发明涉及一种具有体积元件的装置，该体积元件的直径大于与纳米元件外延连接的纳米元件的直径。 体积元件正在被掺杂以便提供高电荷载流子注入纳米元件和电连接中的低访问阻力。 纳米元件可以从半导体衬底直立。 在体积元件上形成的低电阻率材料的同心层形成接触。
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6.发明授权Method of producing precision vertical and horizontal layers in a vertical semiconductor structure 有权在垂直半导体结构中生产精密垂直和水平层的方法公开(公告)号：US08551834B2
公开(公告)日：2013-10-08
申请号：US13458310
申请日：2012-04-27
IPC分类号： H01L21/76
CPC分类号： H01L29/7827 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/495 , H01L29/517 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7828 , H01L29/78642 , H01L33/24 , Y10S977/888 , Y10S977/89
摘要： The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic desposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
摘要翻译： 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。
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7.发明授权Method of producing precision vertical and horizontal layers in a vertical semiconductor structure 有权在垂直半导体结构中制造精密垂直和水平层的方法公开(公告)号：US09087896B2
公开(公告)日：2015-07-21
申请号：US14048502
申请日：2013-10-08
IPC分类号： H01L29/66 , H01L29/78 , B82Y10/00 , H01L29/06 , H01L29/12 , H01L29/775 , H01L29/786 , H01L29/49 , H01L29/51 , H01L33/24
CPC分类号： H01L29/7827 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/495 , H01L29/517 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7828 , H01L29/78642 , H01L33/24 , Y10S977/888 , Y10S977/89
摘要： The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
摘要翻译： 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。
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8.发明申请METHOD OF PRODUCING PRECISION VERTICAL AND HORIZONTAL LAYERS IN A VERTICAL SEMICONDUCTOR STRUCTURE 审中-公开在垂直半导体结构中制造精密垂直层和水平层的方法公开(公告)号：US20140103423A1
公开(公告)日：2014-04-17
申请号：US14048502
申请日：2013-10-08
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/495 , H01L29/517 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7828 , H01L29/78642 , H01L33/24 , Y10S977/888 , Y10S977/89
摘要： The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
摘要翻译： 本发明涉及在垂直半导体器件（1）的垂直和水平表面（15,20）上提供不同厚度的层。 特别地，本发明涉及栅电极和在半导体结构中形成精密层（28），该半导体结构包括基底（10）和基本上从基底上竖立的细长结构（5）。 根据本发明的方法，将装置（1）的垂直几何结构与各向异性沉积或各向异性去除沉积材料结合使用以形成非常高精度的垂直或水平层。
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公开(公告)号：US08350251B1
公开(公告)日：2013-01-08
申请号：US13251555
申请日：2011-10-03
申请人： Truls Lowgren , Ghulam Hasnain
发明人： Truls Lowgren , Ghulam Hasnain
IPC分类号： H01L33/00
CPC分类号： H01L33/405 , H01L33/06 , H01L33/08 , H01L33/18 , H01L33/20 , H01L33/46 , H01L33/60 , H01L2224/48091 , H01L2224/48464 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014
摘要： An opto-electric structure includes a plurality of nano elements arranged side by side on a support layer, where each nano element includes at least a first conductivity type semiconductor nano sized core, and where the core and a second conductivity type semiconductor form a pn or pin junction. A first electrode layer that extends over the plurality of nano elements and is in electrical contact with at least a portion of the second conductivity type semiconductor, and a mirror provided on a second conductivity type semiconductor side of the structure.
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