公开(公告)号：US20090286402A1

公开(公告)日：2009-11-19

申请号：US12257137

申请日：2008-10-23

申请人： Li-Qun Xia ,  Mihaela Balseanu ,  Meiyee Shek ,  Siyi Li ,  Zhenjiang Cui ,  Mehul B. Naik ,  Michael D. Armacost ,  William H. McClintock

发明人： Li-Qun Xia ,  Mihaela Balseanu ,  Meiyee Shek ,  Siyi Li ,  Zhenjiang Cui ,  Mehul B. Naik ,  Michael D. Armacost ,  William H. McClintock

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/02112 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3141 ,  H01L21/31608 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76816

摘要： A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.

摘要翻译： 提供了一种用于在基板中形成窄通孔的方法和装置。 通过常规光刻将图案凹槽蚀刻到基底中。 在衬底的表面上形成薄的共形层，包括图案凹槽的侧壁和底部。 共形层的厚度减小了图案凹槽的有效宽度。 通过各向异性蚀刻从图案凹槽的底部去除共形层以暴露下面的衬底。 然后使用覆盖图案凹槽的侧壁的保形层作为掩模蚀刻衬底。 然后使用湿蚀刻剂除去保形层。

公开(公告)号：US20090140418A1

公开(公告)日：2009-06-04

申请号：US11947638

申请日：2007-11-29

申请人： SIYI LI ,  Li-Qun Xia ,  Michael D. Armacost

发明人： SIYI LI ,  Li-Qun Xia ,  Michael D. Armacost

IPC分类号： H01L21/311 ,  H01L23/48

CPC分类号： H01L21/31116 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/3105 ,  H01L21/31608 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Described herein are methods for integrating low-k dielectric layers with various interconnect structures. In one embodiment, a method for restoring a porous dielectric layer includes forming an opening in the porous low-k dielectric layer. The method further includes forming an opening in a barrier layer. The method further includes depositing a restoring dielectric layer to seal a surface layer of pores of the porous dielectric layer. In one embodiment, the restoring dielectric layer is non-porous and hydrophobic to prevent the porous dielectric layer from adsorbing moisture and consequently increasing the dielectric constant of the porous dielectric layer. The method further includes performing a clean operation on the interconnect structure prior to metallization. The method further includes depositing, masking, and etching a metal layer.

摘要翻译： 这里描述的是用于将低k电介质层与各种互连结构集成的方法。 在一个实施例中，一种用于恢复多孔介电层的方法包括在多孔低k电介质层中形成开口。 该方法还包括在阻挡层中形成开口。 该方法还包括沉积恢复电介质层以密封多孔介电层的孔的表面层。 在一个实施例中，恢复电介质层是无孔的和疏水的，以防止多孔介电层吸附水分，从而增加多孔电介质层的介电常数。 该方法还包括在金属化之前在互连结构上执行清洁操作。 该方法还包括沉积，掩蔽和蚀刻金属层。

公开(公告)号：US07226853B2

公开(公告)日：2007-06-05

申请号：US10197936

申请日：2002-07-16

申请人： Nikolaos Bekiaris ,  Timothy Weidman ,  Michael D. Armacost ,  Mehul B. Naik

发明人： Nikolaos Bekiaris ,  Timothy Weidman ,  Michael D. Armacost ,  Mehul B. Naik

IPC分类号： H01L21/4763

CPC分类号： H01L21/022 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3146 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76835

摘要： A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer; depositing a second hard mask layer on the first hard mask layer; depositing a third hard mask layer on the second hard mask layer and completing formation of the dual damascene structure by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material. In one particular embodiment the second hard mask layer is an amorphous carbon layer and the third hard mask layer is a silicon-containing material.

摘要翻译： 在其上已经形成有电介质层的基板上形成双镶嵌结构的方法。 在一个实施例中，该方法包括在介电层上沉积第一硬掩模层; 在第一硬掩模层上沉积第二硬掩模层; 在第二硬掩模层上沉积第三硬掩模层，并通过蚀刻电介质层中的金属布线图案和通孔图案并用导电材料填充蚀刻的金属布线图案和通孔图案，完成双镶嵌结构的形成。 在一个特定实施例中，第二硬掩模层是无定形碳层，第三硬掩模层是含硅材料。

公开(公告)号：US20100022091A1

公开(公告)日：2010-01-28

申请号：US12180367

申请日：2008-07-25

申请人： SIYI LI ,  Qingjun Zhou ,  Ryan Patz ,  Yifeng Zhou ,  Jeremiah Pender ,  Michael D. Armacost

发明人： SIYI LI ,  Qingjun Zhou ,  Ryan Patz ,  Yifeng Zhou ,  Jeremiah Pender ,  Michael D. Armacost

IPC分类号： H01L21/306

CPC分类号： H01L21/31116 ,  H01J37/3244 ,  H01J37/32449 ,  H01J2237/334 ,  H01L21/31138 ,  H01L21/76808 ,  H01L21/76813

摘要： Described herein are methods and apparatuses for etching low-k dielectric layers to form various interconnect structures. In one embodiment, the method includes forming an opening in a resist layer. The method further includes etching a porous low-k dielectric layer with a process gas mixture that includes a fluorocarbon gas and a carbon dioxide (CO2) gas to form vias. The fluorocarbon gas may be C4F6 gas. A ratio of a flow rate of the C4F6 gas to a flow rate of the CO2 gas can vary from approximately 1:2 to 1:10. In another embodiment, the porous low-k dielectric layer is etched with a process gas mixture that includes a fluorocarbon gas and an argon gas with no CHF3 gas to form trenches aligned with the vias in an integrated dual-damascene structure. The fluorocarbon gas may be CF4 gas.

摘要翻译： 这里描述了用于蚀刻低k电介质层以形成各种互连结构的方法和装置。 在一个实施例中，该方法包括在抗蚀剂层中形成开口。 该方法还包括用包括碳氟化合物气体和二氧化碳（CO 2）气体的工艺气体混合物蚀刻多孔低k电介质层以形成通孔。 碳氟化合物气体可以是C 4 F 6气体。 C4F6气体的流量与CO 2气体的流量的比率可以在约1:2至1:10之间变化。 在另一个实施例中，多孔低k电介质层被包括碳氟化合物气体和没有CHF 3气体的氩气的工艺气体混合物进行蚀刻，以形成与整个双镶嵌结构中的通路对准的沟槽。 碳氟化合物气体可以是CF 4气体。

公开(公告)号：US20080102645A1

公开(公告)日：2008-05-01

申请号：US11555017

申请日：2006-10-31

申请人： Yifeng Zhou ,  Siyi Li ,  Terry Leung ,  Michael D. Armacost

发明人： Yifeng Zhou ,  Siyi Li ,  Terry Leung ,  Michael D. Armacost

IPC分类号： H01L21/3065

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01J37/32706 ,  H01L21/76807

摘要： A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising CO2 is introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is sufficient to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature.

摘要翻译： 包括覆盖电介质特征的抗蚀剂层的衬底在包括天线的衬底处理室以及第一和第二处理电极中被处理。 将包含CO 2 2的工艺气体引入室中。 通过向天线施加源电压并且通过向电极施加具有至少约10MHz的第一频率的第一偏置电压和具有第二频率较小的第二偏置电压来对工艺气体进行通电以形成等离子体 大约4 MHz。 第一偏置电压的功率电平与第二偏置电压的比率足以获得至少约为电介质特征高度的约10％的底层电介质特征的边缘面高度。

公开(公告)号：US07758763B2

公开(公告)日：2010-07-20

申请号：US11555017

申请日：2006-10-31

申请人： Yifeng Zhou ,  Siyi Li ,  Terry Leung ,  Michael D. Armacost

发明人： Yifeng Zhou ,  Siyi Li ,  Terry Leung ,  Michael D. Armacost

IPC分类号： B44C1/22 ,  H01L21/3065

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01J37/32706 ,  H01L21/76807

摘要： A substrate comprising a resist layer overlying a dielectric feature, is processed in a substrate processing chamber comprising an antenna, and first and second process electrodes. A process gas comprising CO2 is introduced into the chamber. The process gas is energized to form a plasma by applying a source voltage to the antenna, and by applying to the electrodes, a first bias voltage having a first frequency of at least about 10 MHz and a second bias voltage having a second frequency of less than about 4 MHz. The ratio of the power level of the first bias voltage to the second bias voltage is sufficient to obtain an edge facet height of the underlying dielectric feature that is at least about 10% of the height of the dielectric feature.

摘要翻译： 包括覆盖电介质特征的抗蚀剂层的衬底在包括天线的衬底处理室以及第一和第二处理电极中被处理。 将包含CO 2的工艺气体引入室中。 通过向天线施加源电压并且通过向电极施加具有至少约10MHz的第一频率的第一偏置电压和具有第二频率较小的第二偏置电压来对工艺气体进行通电以形成等离子体 大约4 MHz。 第一偏置电压的功率电平与第二偏置电压的比率足以获得至少约为电介质特征高度的约10％的底层电介质特征的边缘面高度。

公开(公告)号：US20100043821A1

公开(公告)日：2010-02-25

申请号：US12193964

申请日：2008-08-19

申请人： Siyi Li ,  Ryan Patz ,  Qingjun Zhou ,  Jeremiah Pender ,  Michael D. Armacost

发明人： Siyi Li ,  Ryan Patz ,  Qingjun Zhou ,  Jeremiah Pender ,  Michael D. Armacost

IPC分类号： B08B6/00

CPC分类号： H01L21/31138 ,  G03F7/427 ,  H01L21/76808

摘要： Described herein are methods and apparatus for removing photoresist in the presence of low-k dielectric layers. In one embodiment, the method includes exciting a first mixture of gases having a ratio of a flow rate of reducing process gas to a flow rate of an oxygen-containing process gas that is between 1:1 and 100:1 to generate a first reactive gas mixture. Next, the method includes exposing the photoresist layer that overlays the low-k dielectric layer on a substrate to the first reactive gas mixture to selectively remove the photoresist layer from the dielectric layer. Next, the method includes exposing the photoresist layer to a second reactive gas mixture to selectively remove the photoresist layer from the dielectric layer. The first and second reactive gas mixtures contain substantially no ions when the substrate is exposed to these mixtures in order to minimize damage to the low-k dielectric layer.

摘要翻译： 这里描述了在低k电介质层的存在下去除光致抗蚀剂的方法和装置。 在一个实施方案中，该方法包括激发第一混合气体，其中还原过程气体的流量与含氧处理气体的流量之比在1:1至100:1之间以产生第一反应性 气体混合物 接下来，该方法包括将衬底上的低k电介质层覆盖的光致抗蚀剂层暴露于第一反应气体混合物，以从电介质层选择性地除去光致抗蚀剂层。 接下来，该方法包括将光致抗蚀剂层暴露于第二反应气体混合物以从介质层选择性地除去光致抗蚀剂层。 当基板暴露于这些混合物时，第一和第二反应气体混合物基本上不含离子，以便最小化对低k电介质层的损伤。

公开(公告)号：US07115534B2

公开(公告)日：2006-10-03

申请号：US10847891

申请日：2004-05-18

申请人： Son Van Nguyen ,  Michael D. Armacost ,  Mehul Naik ,  Girish A. Dixit ,  Ellie Y. Yieh

发明人： Son Van Nguyen ,  Michael D. Armacost ,  Mehul Naik ,  Girish A. Dixit ,  Ellie Y. Yieh

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76808

摘要： Methods are provided for depositing a dielectric material for use as an anti-reflective coating and sacrificial dielectric material in damascene formation. In one aspect, a process is provided for processing a substrate including depositing an acidic dielectric layer on the substrate by reacting an oxygen-containing organosilicon compound and an acidic compound, depositing a photoresist material on the acidic dielectric layer, and patterning the photoresist layer. The acidic dielectric layer may be used as a sacrificial layer in forming a feature definition by etching a partial feature definition, depositing the acidic dielectric material, etching the remainder of the feature definition, and then removing the acidic dielectric material to form a feature definition.

摘要翻译： 提供了用于沉积电介质材料的方法，用作防蚀涂层和牺牲电介质材料在镶嵌形成中。 在一个方面，提供了一种处理衬底的方法，包括通过使含氧有机硅化合物和酸性化合物反应，在酸性电介质层上沉积光致抗蚀剂材料，并使光致抗蚀剂层图形化，在衬底上沉积酸性介电层。 通过蚀刻部分特征定义，沉积酸性电介质材料，蚀刻特征定义的其余部分，然后除去酸性介电材料以形成特征定义，可以将酸性介电层用作形成特征定义的牺牲层。

公开(公告)号：US06829056B1

公开(公告)日：2004-12-07

申请号：US10646943

申请日：2003-08-21

申请人： Michael Barnes ,  John Holland ,  Hongqing Shan ,  Bryan Y. Pu ,  Mohit Jain ,  Zhifeng Sui ,  Michael D. Armacost ,  Neil E. Hanson ,  Diana Xiaobing Ma ,  Ashok K. Sinha ,  Dan Maydan

发明人： Michael Barnes ,  John Holland ,  Hongqing Shan ,  Bryan Y. Pu ,  Mohit Jain ,  Zhifeng Sui ,  Michael D. Armacost ,  Neil E. Hanson ,  Diana Xiaobing Ma ,  Ashok K. Sinha ,  Dan Maydan

IPC分类号： G01B1114

CPC分类号： H01L21/67253 ,  H01J37/32935 ,  H01L21/67069

摘要： A substrate processing apparatus has a chamber having a substrate support, gas distributor, gas energizer, and gas exhaust port. A process monitor is provided to monitor features in a first region of the substrate and generate a corresponding first signal, and to monitor features in a second region of the substrate and generate a second signal. A chamber controller receives and evaluates the first and second signals, and operates the chamber in relation to the signals. For example, the chamber controller can select a process recipe depending upon the signal values. The chamber controller can also set a process parameter at a first level in a first processing sector and at a second level in a second processing sector. The apparatus provides a closed control loop to independently monitor and control processing of features at different regions of the substrate.

摘要翻译： 基板处理装置具有具有基板支撑件，气体分配器，气体激励器和排气口的腔室。 提供过程监视器以​​监测衬底的第一区域中的特征并产生相应的第一信号，并且监测衬底的第二区域中的特征并产生第二信号。 室控制器接收并评估第一和第二信号，并相对于信号操作室。 例如，腔室控​​制器可以根据信号值选择工艺配方。 腔室控制器还可以在第一处理扇区中将处理参数设置在第一电平处，并在第二处理扇区中将第二电平设置为第二电平。 该装置提供一个闭合的控制回路以独立地监测和控制基板的不同区域处的特征的处理。

公开(公告)号：US06750113B2

公开(公告)日：2004-06-15

申请号：US09764832

申请日：2001-01-17

申请人： Michael D. Armacost ,  Andreas K. Augustin ,  Gerald R. Friese ,  John E. Heidenreich, III ,  Gary R. Hueckel ,  Kenneth J. Stein

发明人： Michael D. Armacost ,  Andreas K. Augustin ,  Gerald R. Friese ,  John E. Heidenreich, III ,  Gary R. Hueckel ,  Kenneth J. Stein

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

摘要翻译： 在铜技术中的平行平板电容器形成在其下方没有铜（0.3μm以下）的区域中，底部蚀刻停止层，在TiN层下方具有铝层的复合底板，氧化物电容器电介质和 TiN顶板; 在包括蚀刻顶板以留下电容器区域的过程中，将底板蚀刻到具有在所有侧面上的边缘的较大底部区域; 在电容器顶板的顶表面下沉积具有较高材料质量的层间电介质; 打开接触孔到顶板和底板，并且将互连件下降到两步工艺，其在穿过底板上方的氮化物盖层之后部分地打开下互连和顶板上的氮化物盖层，然后切穿电容器电介质 并完成氮化物盖层的穿透。