公开(公告)号：US20160204053A1

公开(公告)日：2016-07-14

申请号：US14861423

申请日：2015-09-22

Applicant: MediaTek Inc.

Inventor： Tung-Hsien HSIEH ,  Yi-Hui LEE

IPC: H01L23/495 ,  H05K1/02

CPC classification number: H01L23/49503 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/1421 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0215 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die peddle. A supporting bar connects to the die peddle, extending in an outward direction from the die peddle. At least two power leads are separated from the die peddle and the supporting bar, having first terminals close to the die peddle and second terminals extending outward from the die peddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括包括模具的引线框架。 支撑杆连接到模具，从模具向外延伸。 至少两个电源引线与模具和支撑杆分离，支撑杆具有靠近模具的第一端子，并且从模具踏板向外延伸的第二端子。 电源杆连接到具有支撑部分的至少两个电源引线。 成型材料封装引线框架，使支撑部分露出。

公开(公告)号：US20160260659A1

公开(公告)日：2016-09-08

申请号：US15048807

申请日：2016-02-19

Applicant: MediaTek Inc.

Inventor： Tung-Hsien HSIEH ,  Che-Ya CHOU

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括再分配层（RDL）结构裸片附着表面和与裸片附着表面相对的凸起附着表面。 半导体管芯安装在再分配层（RDL）结构的管芯附接表面上。 第一焊料掩模层设置在裸片附着表面上。 第一焊料掩模层围绕半导体管芯。 附加电路结构设置在第一焊料掩模的围绕半导体管芯的部分上。 附加电路结构包括具有第一宽度的焊盘部分和通孔部分具有小于第一宽度的第二宽度。 通孔部分穿过第一焊料掩模层以耦合再分布层（RDL）结构。

公开(公告)号：US20130277801A1

公开(公告)日：2013-10-24

申请号：US13790097

申请日：2013-03-08

Applicant: MEDIATEK INC.

Inventor： Nan-Cheng CHEN ,  Tung-Hsien HSIEH

IPC: H01L23/522

CPC classification number: H01L23/5223 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L25/105 ,  H01L27/0248 ,  H01L27/1255 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: According to an embodiment of the invention, a chip package is provided. The chip package includes: a lower chip package; an upper chip package disposed on an upper surface of the lower chip package; at least one conducting element disposed between the lower chip package and the upper chip package; and at least one decoupling capacitor disposed on the upper surface of the lower chip package, wherein the decoupling capacitor is not covered by the upper chip package, and the decoupling capacitor is electrically connected to a power line or a ground line in the lower chip package.

Abstract translation: 根据本发明的实施例，提供了芯片封装。 芯片封装包括：一个较低的芯片封装; 上芯片封装，设置在下芯片封装的上表面上; 设置在下芯片封装和上芯片封装之间的至少一个导电元件; 以及设置在下芯片封装的上表面上的至少一个去耦电容器，其中去耦电容器不被上芯片封装覆盖，并且去耦电容器电连接到下芯片封装中的电源线或接地线 。

公开(公告)号：US20170271250A1

公开(公告)日：2017-09-21

申请号：US15613333

申请日：2017-06-05

Applicant: MEDIATEK Inc.

Inventor： Tung-Hsien HSIEH ,  Che-Ya CHOU

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Various structures of a semiconductor package assembly are provided. In one implementation, a semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer disposed on the die-attach surface, surrounding the semiconductor die. Further, a first conductive bump disposed over the first solder mask, coupled to a first pad of the redistribution layer (RDL) structure through a single circuit structure on a portion the first solder mask layer, wherein a first distance between a center of the first pad and a sidewall of the semiconductor die, which is close to the first pad, is equal to or greater than a second distance between a center of the first conductive bump and the sidewall of the semiconductor die.

公开(公告)号：US20220196706A1

公开(公告)日：2022-06-23

申请号：US17509347

申请日：2021-10-25

Applicant: MEDIATEK INC.

Inventor： Tung-Hsien HSIEH

IPC: G01R1/073 ,  G01R31/28

Abstract: A probe card assembly includes a circuit board, a substrate, and at least one passive component. The substrate is disposed opposite and connected to the circuit board. The circuit board has a first opening facing the substrate and/or the substrate has a second opening facing the circuit board. The at least one passive component is disposed between the circuit board and the substrate and is at least partially accommodated in at least one of the first opening and the second opening.

公开(公告)号：US20140042615A1

公开(公告)日：2014-02-13

申请号：US13933259

申请日：2013-07-02

Applicant: MediaTek Inc.

Inventor： Ching-Liou HUANG ,  Tung-Hsien HSIEH ,  Che-Ya CHOU

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06133 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16013 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An exemplary flip-chip package is provided, including: a package structure having a first bonding pad and a second bonding pad formed thereon, wherein the first bond pad has a feature size different from a feature size of the second bond pad; a semiconductor chip facing the package structure, having a first under bump metal (UBM) layer and a second under bump metal (UBM) layer formed thereon, wherein the first UBM layer has a feature size different from a feature size of the second UBM layer; a first conductive element disposed between the first bond pad and the first UBM layer; and a second conductive element disposed between the second bond pad and the second UBM layer.

Abstract translation: 提供了一种示例性的倒装芯片封装，其包括：封装结构，其具有形成在其上的第一焊盘和第二焊盘，其中所述第一接合焊盘具有与所述第二接合焊盘的特征尺寸不同的特征尺寸; 面向封装结构的半导体芯片，具有形成在其上的第一下凸块金属（UBM）层和第二下凸块金属（UBM）层，其中第一UBM层具有与第二UBM层的特征尺寸不同的特征尺寸 ; 设置在所述第一接合焊盘和所述第一UBM层之间的第一导电元件; 以及设置在所述第二接合焊盘和所述第二UBM层之间的第二导电元件。

公开(公告)号：US20140264812A1

公开(公告)日：2014-09-18

申请号：US14188881

申请日：2014-02-25

Applicant: MediaTek Inc.

Inventor： Sheng-Ming CHANG ,  Tung-Hsien HSIEH ,  Nan-Cheng CHEN

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15183 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first body having a first device-attach surface and a first bump-attach surface opposite to the first device-attach surface. A second semiconductor package is bonded to the first device-attach surface of the first semiconductor package. The second package includes a second body having a second device-attach surface and a second bump-attach surface opposite to the second device-attach surface. A dynamic random access memory (DRAM) device is mounted on the second device-attach surface. A decoupling capacitor is mounted on the second device-attach surface. Conductive structures are disposed on the second bump-attach surface of the second package, connecting to the first bump-attach surface of the first body of the first semiconductor package.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括具有第一器件附着表面和与第一器件附着表面相对的第一凸起附着表面的第一本体。 第二半导体封装被结合到第一半导体封装的第一器件附着表面。 第二包装包括具有第二装置附着表面的第二主体和与第二装置附接表面相对的第二凸起附着表面。 动态随机存取存储器（DRAM）装置安装在第二装置附接表面上。 去耦电容器安装在第二器件附着表面上。 导电结构设置在第二封装的第二凸起附接表面上，连接到第一半导体封装的第一主体的第一凸起附着表面。