公开(公告)号：US20050087490A1

公开(公告)日：2005-04-28

申请号：US10695374

申请日：2003-10-28

申请人： Mark Chace ,  Jeffrey Hedrick ,  Habib Hichri ,  Keith Pope ,  Jia Lee ,  Kelly Malone ,  Kenneth McCullough ,  Wayne Moreau ,  Darryl Restaino ,  Shahab Siddiqui

发明人： Mark Chace ,  Jeffrey Hedrick ,  Habib Hichri ,  Keith Pope ,  Jia Lee ,  Kelly Malone ,  Kenneth McCullough ,  Wayne Moreau ,  Darryl Restaino ,  Shahab Siddiqui

IPC分类号： B01D11/04 ,  B01D11/00

CPC分类号： B01D11/0407

摘要： A process of removing impurities from a cured low dielectric constant organic polymeric film disposed on a semiconductor device. The process involves disposing a low dielectric constant curable organic polymeric film on an electrically conductive surface of a semiconductor device. The organic polymeric film is cured on the semiconductor device and thereupon contacted with supercritical carbon dioxide, optionally in the presence of at least one cosolvent.

摘要翻译： 从设置在半导体器件上的固化的低介电常数有机聚合物膜去除杂质的方法。 该方法包括将低介电常数可固化有机聚合物膜设置在半导体器件的导电表面上。 有机聚合物膜在半导体器件上固化，随后与超临界二氧化碳接触，任选地在至少一种助溶剂的存在下。

公开(公告)号：US20090117360A1

公开(公告)日：2009-05-07

申请号：US11933760

申请日：2007-11-01

申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

IPC分类号： G03C1/73 ,  B05D3/00 ,  B32B27/06

CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  H01L21/0338

摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.

摘要翻译： 含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。 将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。 在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。 聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。 两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。

公开(公告)号：US06806182B2

公开(公告)日：2004-10-19

申请号：US10137274

申请日：2002-05-01

申请人： Darryl Restaino ,  Shahab Siddiqui ,  Erdem Kaltalioglu ,  Delores Bennett ,  Chih-Chih Liu ,  Hsueh-Chung Chen ,  Tong-Yu Chen ,  Gwo-Shii Yang ,  Chiung-Sheng Hsiung

发明人： Darryl Restaino ,  Shahab Siddiqui ,  Erdem Kaltalioglu ,  Delores Bennett ,  Chih-Chih Liu ,  Hsueh-Chung Chen ,  Tong-Yu Chen ,  Gwo-Shii Yang ,  Chiung-Sheng Hsiung

IPC分类号： H01L214763

CPC分类号： H01L21/02252 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02304 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834

摘要： Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

摘要翻译： 在覆盖有机层间介质之前，将粘合促进剂施加到覆盖层和粘附促进剂的氧化之后，减少了体现多层金属和有机层间电介质的半导体晶片的热循环过程中的电阻问题。

公开(公告)号：US08809152B2

公开(公告)日：2014-08-19

申请号：US13300146

申请日：2011-11-18

申请人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

发明人： MaryJane Brodsky ,  Murshed M. Chowdhury ,  Michael P. Chudzik ,  Min Dai ,  Siddarth A. Krishnan ,  Shreesh Narasimha ,  Shahab Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L29/518 ,  H01L21/28255 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

摘要翻译： 一种半导体器件，包括在所述半导体衬底的沟道区上包括栅极结构的含锗衬底。 栅极结构可以包括与含锗衬底的上表面直接接触的氧化硅层，与氧化硅层直接接触的至少一个高k栅介质层和直接与锗氧化物层直接接触的至少一个栅极导体 与高k栅介质层接触。 氧化硅层和含锗衬底的上表面之间的界面基本上不含氧化锗。 源极区域和漏极区域可以存在于沟道区域的相对侧上。

公开(公告)号：US20140001575A1

公开(公告)日：2014-01-02

申请号：US13534012

申请日：2012-06-27

申请人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

发明人： Charlotte DeWan Adams ,  Michael P. Chudzik ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of manufacturing multiple finFET devices having different thickness gate oxides. The method may include depositing a first dielectric layer on top of the semiconductor substrate, on top of a first fin, and on top of a second fin; forming a first dummy gate stack; forming a second dummy gate stack; removing the first and second dummy gates selective to the first and second gate oxides; masking a portion of the semiconductor structure comprising the second fin, and removing the first gate oxide from atop the first fin; and depositing a second dielectric layer within the first opening, and within the second opening, the second dielectric layer being located on top of the first fin and adjacent to the exposed sidewalls of the first pair of dielectric spacers, and on top of the second gate oxide and adjacent to the exposed sidewalls of the second pair of dielectric spacers.

摘要翻译： 制造具有不同厚度栅极氧化物的多个finFET器件的方法。 该方法可以包括在半导体衬底的顶部上，在第一鳍的顶部上并在第二鳍的顶部上沉积第一介电层; 形成第一虚拟栅极堆叠; 形成第二虚拟栅极叠层; 去除对第一和第二栅极氧化物选择性的第一和第二伪栅极; 掩蔽包括第二鳍片的半导体结构的一部分，并且从第一鳍片顶部去除第一栅极氧化物; 以及在所述第一开口内沉积第二电介质层，并且在所述第二开口内，所述第二电介质层位于所述第一散热片的顶部并且邻近所述第一对电介质间隔件的暴露的侧壁，并且在所述第二栅极的顶部 氧化物并且与第二对电介质间隔物的暴露的侧壁相邻。

公开(公告)号：US20130330843A1

公开(公告)日：2013-12-12

申请号：US13490740

申请日：2012-06-07

申请人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui

发明人： Michael P. Chudzik ,  Min Dai ,  Jinping Liu ,  Paul A. Ronsheim ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui

IPC分类号： H01L21/66 ,  G06F17/50

CPC分类号： H01L29/513 ,  H01L21/28185 ,  H01L21/28202 ,  H01L22/12 ,  H01L22/26 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.

摘要翻译： 公开了一种形成半导体器件的方法。 该方法包括：在基板上形成电介质区域; 在包括氨（NH 3）在内的环境中退火电介质区域; 在退火期间监测所述衬底和所述电介质区域中的至少一个的氮峰; 并根据氮峰的监测来调整环境参数。

公开(公告)号：US08431476B2

公开(公告)日：2013-04-30

申请号：US13570980

申请日：2012-08-09

申请人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

发明人： Joel P. de Souza ,  Keith E. Fogel ,  Edward W. Kiewra ,  Steven J. Koester ,  Christopher C. Parks ,  Devendra K. Sadana ,  Shahab Siddiqui

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L21/28264 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 Å to 400 Å on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

公开(公告)号：US20120329230A1

公开(公告)日：2012-12-27

申请号：US13164891

申请日：2011-06-21

申请人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Jinping Liu

发明人： Michael P. Chudzik ,  Min Dai ,  Joseph F. Shepard, JR. ,  Shahab Siddiqui ,  Jinping Liu

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/02052 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28211 ,  H01L21/28238

摘要： A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 Å to 10 Å.

摘要翻译： 一种制造含硅氧化物层的方法，包括在半导体衬底的表面上提供化学氧化物层，在1000℃或更高的温度下在无氧环境中除去化学氧化物层，以提供裸露 在半导体衬底的表面上，以1000℃的温度将半导体衬底的裸露表面的含氧气体首次引入半导体衬底的裸露表面。然后在第二时间内将温度降至室温 同时保持含氧气体的流速，从而提供厚度范围从0.5到10的含硅氧化物层。

公开(公告)号：US20120171818A1

公开(公告)日：2012-07-05

申请号：US13418716

申请日：2012-03-13

申请人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ricardo A. Donaton ,  Spyridon Galis ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L21/50

CPC分类号： H01L23/5389 ,  H01L21/76898 ,  H01L24/80 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2924/12044

摘要： Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

摘要翻译： 第一基板和第二基板中的每一个包括具有耐扩散电介质材料如氮化硅的表面。 凹陷区域形成在耐扩散电介质材料中，并且填充有可粘结介电材料。 第一和第二基板中的金属焊盘和可接合的介质材料部分的图案可以具有镜面对称性。 第一和第二基板通过金属焊盘和可接合的介电材料部分之间的触点之间的触点进行物理接触和接合。 通过基底通孔（TSV）结构通过键合介电材料部分形成。 位于TSV结构周围的每对键合的电介质材料部分之间的界面由两个扩散电阻的介电材料层封装，使得接合界面处的金属的扩散被包含在每对键合介电材料部分内。

公开(公告)号：US20090001592A1

公开(公告)日：2009-01-01

申请号：US11770928

申请日：2007-06-29

申请人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

发明人： Karl W. Barth ,  Ramona Kei ,  Kaushik A. Kumar ,  Kevin S. Petrarca ,  Shahab Siddiqui

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming a metal interconnect and an IC chip including the metal interconnect are disclosed. One embodiment of the method may include providing an integrated circuit (IC) chip up to and including a middle of line (MOL) layer, the MOL layer including a contact positioned within a first dielectric; recessing the first dielectric such that the contact extends beyond an upper surface of the first dielectric; forming a second dielectric over the first dielectric such that the second dielectric surrounds at least a portion of the contact, the second dielectric having a lower dielectric constant than the first dielectric; forming a planarizing layer over the second dielectric; forming an opening through the planarizing layer and into the second dielectric to the contact; and forming a metal in the opening to form the metal interconnect.

摘要翻译： 公开了形成金属互连的方法和包括金属互连的IC芯片。 该方法的一个实施例可以包括提供直到并包括中间线（MOL）层的集成电路（IC）芯片，MOL层包括定位在第一电介质内的触点; 使第一电介质凹陷，使得接触延伸超过第一电介质的上表面; 在所述第一电介质上形成第二电介质，使得所述第二电介质围绕所述接触的至少一部分，所述第二电介质具有比所述第一电介质更低的介电常数; 在所述第二电介质上形成平坦化层; 通过平坦化层形成开口并进入到接触件的第二电介质中; 并在开口中形成金属以形成金属互连。