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19 条记录 (耗时 0.018 秒)

    Method for forming metallization structure having flat surface on semiconductor substrate
    2.
    发明授权
    Method for forming metallization structure having flat surface on semiconductor substrate 失效
    在半导体衬底上形成具有平坦表面的金属化结构的方法

    公开(公告)号：US4520041A

    公开(公告)日：1985-05-28

    申请号：US548440

    申请日：1983-11-03

    申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

    发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

    IPC分类号： H01L21/3205 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532 ,  H01L21/283 ,  H01L21/302

    CPC分类号： H01L23/53295 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002

    摘要： A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.

    摘要翻译： 通过在衬底上形成第一绝缘层和第二绝缘层，可以在半导体衬底上形成具有基本平坦表面的金属化结构。 选择性地去除第二绝缘层以在其中形成凹槽。 然后，顺应地形成金属材料层。 金属层具有与第二绝缘层的槽对应的槽。 将可流动的聚合物施加到所得结构的表面以形成具有平坦表面的层。 依次离子蚀刻聚合物层和金属层以露出第二绝缘层。 因此，由剩余的金属层和第二绝缘层构成的金属化结构形成为具有平坦的表面。

    Semiconductor device having a multilayer wiring structure using a polyimide resin
    3.
    发明授权
    Semiconductor device having a multilayer wiring structure using a polyimide resin 失效
    具有使用聚酰亚胺树脂的多层布线结构的半导体装置

    公开(公告)号：US4618878A

    公开(公告)日：1986-10-21

    申请号：US621086

    申请日：1984-06-15

    申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

    发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

    IPC分类号： H01L21/768 ,  H01L21/31 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

    CPC分类号： H01L23/5329 ,  H01L2924/0002

    摘要： A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.

    摘要翻译： 一种具有多层布线结构的半导体器件，包括半导体衬底，沉积在所述衬底上的第一布线层和沉积在所述第一布线层上的绝缘层的第二布线层，其中绝缘中间层由无机绝缘层 以及覆盖无机绝缘层的聚酰亚胺系树脂膜。 聚酰亚胺系树脂膜与无机绝缘膜的厚度比为0.1〜0.5。 一种制造多层布线结构的半导体器件的方法，其中在绝缘中间层中形成具有小台阶的开口。

    System for etching a metal film on a semiconductor wafer
    4.
    发明授权
    System for etching a metal film on a semiconductor wafer 失效
    用于蚀刻半导体晶片上的金属膜的系统

    公开(公告)号：US4462856A

    公开(公告)日：1984-07-31

    申请号：US467298

    申请日：1983-02-17

    申请人： Masahiro Abe ,  Toshio Yonezawa ,  Masaharu Aoyama ,  Takashi Ajima

    发明人： Masahiro Abe ,  Toshio Yonezawa ,  Masaharu Aoyama ,  Takashi Ajima

    IPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/3213 ,  C23F1/02 ,  C25F3/04 ,  C25F3/12

    CPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/32134

    摘要： A system is adapted to etch an aluminium film on a semiconductor wafer into a predetermined pattern by immersing the film in an etching solution. The system comprises a voltage detecting circuit for detecting a voltage created between a platinum electrode and the aluminium film on the semiconductor wafer which are immersed in the etching solution, a comparator for comparing a reference voltage with the voltage detected by the voltage detecting circuit to produce an output signal, and a timer for starting a time count operation upon receipt of the output signal from the comparator and for producing an etching completion signal when it continuously receives the output signal from the comparator for a predetermined time period.

    摘要翻译： 系统适于通过将膜浸入蚀刻溶液中将半导体晶片上的铝膜蚀刻成预定图案。 该系统包括电压检测电路，用于检测浸在蚀刻溶液中的铂电极和半导体晶片上的铝膜之间产生的电压;比较器，用于将参考电压与由电压检测电路检测到的电压进行比较，以产生 输出信号，以及在从比较器接收到输出信号时开始时间计数操作的定时器，并且当其在预定时间段内连续接收来自比较器的输出信号时产生蚀刻完成信号。

    Semiconductor device with multi-layered metalizations
    8.
    发明授权
    Semiconductor device with multi-layered metalizations 失效
    具有多层金属化的半导体器件

    公开(公告)号：US4200969A

    公开(公告)日：1980-05-06

    申请号：US831873

    申请日：1977-09-09

    申请人： Masaharu Aoyama ,  Shunichi Hiraki ,  Toshio Yonezawa

    发明人： Masaharu Aoyama ,  Shunichi Hiraki ,  Toshio Yonezawa

    IPC分类号： H01L21/3205 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  B01J17/00

    CPC分类号： H01L21/76838 ,  H01L21/32134 ,  H01L21/32136 ,  Y10S438/945 ,  Y10T29/49156

    摘要： There are provided a semiconductor device having alternately layered insulating and conductive layers on the major surface of a semiconductor body and the process for manufacturing the semiconductor device. In the manufacturing process, the conductive layers other than the conductive layer finally formed are each formed to be a laminate including at least two metal layers of which the etching rates are different. The photo-engraving process follows this step. In the lamina, the metal layer closer to the semiconductor body has a lower etching rate than that of the metal layer formed thereover. In the semiconductor device, the conductive layer other than that disposed furthest away from the semiconductor body has its side wall diverged to widen toward the semiconductor body.

    摘要翻译： 提供了一种在半导体主体的主表面上具有交替层叠的绝缘和导电层的半导体器件和用于制造半导体器件的工艺。 在制造过程中，最终形成的导电层以外的导电层各自形成为包括蚀刻速率不同的至少两个金属层的层压体。 照相雕刻过程遵循此步骤。 在薄层中，更靠近半导体本体的金属层的蚀刻速率比形成在其上的金属层的蚀刻速率低。 在半导体器件中，除了远离半导体主体的导电层之外的导电层的侧壁发散，朝向半导体本体变宽。