公开(公告)号：US4618878A

公开(公告)日：1986-10-21

申请号：US621086

申请日：1984-06-15

申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/768 ,  H01L21/31 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.

摘要翻译： 一种具有多层布线结构的半导体器件，包括半导体衬底，沉积在所述衬底上的第一布线层和沉积在所述第一布线层上的绝缘层的第二布线层，其中绝缘中间层由无机绝缘层 以及覆盖无机绝缘层的聚酰亚胺系树脂膜。 聚酰亚胺系树脂膜与无机绝缘膜的厚度比为0.1〜0.5。 一种制造多层布线结构的半导体器件的方法，其中在绝缘中间层中形成具有小台阶的开口。

公开(公告)号：US4462856A

公开(公告)日：1984-07-31

申请号：US467298

申请日：1983-02-17

申请人： Masahiro Abe ,  Toshio Yonezawa ,  Masaharu Aoyama ,  Takashi Ajima

发明人： Masahiro Abe ,  Toshio Yonezawa ,  Masaharu Aoyama ,  Takashi Ajima

IPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/3213 ,  C23F1/02 ,  C25F3/04 ,  C25F3/12

CPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/32134

摘要： A system is adapted to etch an aluminium film on a semiconductor wafer into a predetermined pattern by immersing the film in an etching solution. The system comprises a voltage detecting circuit for detecting a voltage created between a platinum electrode and the aluminium film on the semiconductor wafer which are immersed in the etching solution, a comparator for comparing a reference voltage with the voltage detected by the voltage detecting circuit to produce an output signal, and a timer for starting a time count operation upon receipt of the output signal from the comparator and for producing an etching completion signal when it continuously receives the output signal from the comparator for a predetermined time period.

摘要翻译： 系统适于通过将膜浸入蚀刻溶液中将半导体晶片上的铝膜蚀刻成预定图案。 该系统包括电压检测电路，用于检测浸在蚀刻溶液中的铂电极和半导体晶片上的铝膜之间产生的电压;比较器，用于将参考电压与由电压检测电路检测到的电压进行比较，以产生 输出信号，以及在从比较器接收到输出信号时开始时间计数操作的定时器，并且当其在预定时间段内连续接收来自比较器的输出信号时产生蚀刻完成信号。

公开(公告)号：US4520041A

公开(公告)日：1985-05-28

申请号：US548440

申请日：1983-11-03

申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/3205 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532 ,  H01L21/283 ,  H01L21/302

CPC分类号： H01L23/53295 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002

摘要： A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.

摘要翻译： 通过在衬底上形成第一绝缘层和第二绝缘层，可以在半导体衬底上形成具有基本平坦表面的金属化结构。 选择性地去除第二绝缘层以在其中形成凹槽。 然后，顺应地形成金属材料层。 金属层具有与第二绝缘层的槽对应的槽。 将可流动的聚合物施加到所得结构的表面以形成具有平坦表面的层。 依次离子蚀刻聚合物层和金属层以露出第二绝缘层。 因此，由剩余的金属层和第二绝缘层构成的金属化结构形成为具有平坦的表面。

公开(公告)号：US4636832A

公开(公告)日：1987-01-13

申请号：US837663

申请日：1986-03-04

申请人： Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/532 ,  H01L23/14

CPC分类号： H01L24/85 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/19043 ,  H01L2924/20752

摘要： A semiconductor device with a bonding section comprising a semiconductor substrate, a silicon layer formed on the semiconductor substrate with a first insulating layer interposed therebetween, and a bonding pad formed on the silicon layer with a second insulating layer interposed therebetween. The silicon layer has substantially the same size as the bonding pad. When a lead line is bonded to the bonding pad, the silicon layer lessens the stress caused by the bonding.

摘要翻译： 一种具有接合部分的半导体器件，包括半导体衬底，在半导体衬底上形成有第一绝缘层的硅层，以及形成在硅层上并具有介于其间的第二绝缘层的接合焊盘。 硅层具有与焊盘大致相同的尺寸。 当引线与接合焊盘接合时，硅层减小由接合引起的应力。

公开(公告)号：US4415372A

公开(公告)日：1983-11-15

申请号：US313332

申请日：1981-10-20

申请人： Yutaka Koshino ,  Toshio Yonezawa ,  Takashi Ajima ,  Jiro Ohshima

发明人： Yutaka Koshino ,  Toshio Yonezawa ,  Takashi Ajima ,  Jiro Ohshima

IPC分类号： H01L21/263 ,  H01L21/265 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L21/2636 ,  H01L21/26513 ,  Y10S148/046

摘要： The invention provides a method for fabricating a semiconductor device which comprises the steps of ion-implanting an impurity into a monocrystalline semiconductor substrate; irradiating the region into which the impurity ions have been implanted with an accelerated electron beam under the conditions that the acceleration voltage is 20 to 200 KeV, and the current is 0.01 to 1 mA and the exposure dose is 10.sup.20 to 10.sup.15 /cm.sup.2 ; and carrying out annealing to form a semiconductor region of one conductivity type. According to the present invention, a semiconductor device can be fabricated which has fewer lattice defects and in which the lifetime of the carriers is long.

摘要翻译： 本发明提供一种制造半导体器件的方法，该方法包括以下步骤：将杂质离子注入到单晶半导体衬底中; 在加速电压为20〜200KeV，电流为0.01〜1mA，曝光量为1020〜1015 / cm2的条件下，用加速电子束照射杂质离子注入的区域; 并进行退火以形成一种导电类型的半导体区域。 根据本发明，可以制造具有更少的晶格缺陷并且其中载体的寿命长的半导体器件。

公开(公告)号：US4224636A

公开(公告)日：1980-09-23

申请号：US915542

申请日：1978-06-14

申请人： Toshio Yonezawa ,  Takashi Ajima ,  Masato Uchida

发明人： Toshio Yonezawa ,  Takashi Ajima ,  Masato Uchida

IPC分类号： H01L21/314 ,  H01L23/29 ,  H01L23/31 ,  H01L29/34

CPC分类号： H01L23/3171 ,  H01L21/314 ,  H01L23/291 ,  H01L23/3192 ,  H01L2924/0002

摘要： A semiconductor device comprising a semiconductor substrate and protective films formed thereon. The protective films comprise at least one silicon carbide film which may be pure or may contain particular impurities.

摘要翻译： 一种半导体器件，包括半导体衬底和形成在其上的保护膜。 保护膜包括至少一个可以是纯的或可能含有特定杂质的碳化硅膜。

公开(公告)号：US4146413A

公开(公告)日：1979-03-27

申请号：US738059

申请日：1976-11-02

申请人： Toshio Yonezawa ,  Toshio Mitsuno ,  Kiyoshi Takaoki ,  Takashi Ajima

发明人： Toshio Yonezawa ,  Toshio Mitsuno ,  Kiyoshi Takaoki ,  Takashi Ajima

IPC分类号： H01L29/78 ,  H01L21/205 ,  H01L21/225 ,  H01L21/28 ,  H01L21/321 ,  H01L29/04 ,  H01L29/43 ,  H01L29/861 ,  H01L21/20

CPC分类号： H01L21/321 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/04 ,  Y10S148/124

摘要： A method of producing a semiconductor device, comprising the steps of forming a polycrystalline semiconductor layer on the exposed surface of a single crystalline semiconductor substrate, the substrate containing an impurity of one conductivity type and the polycrystalline layer an impurity of the other conductivity type, and heating the polycrystalline layer for the activation thereof at a temperature substantially preventing the impurity contained therein from being diffused into the substrate. The crystal of the substrate is kept free from lattice defect since the impurity is not diffused thereinto. In addition, this method prevents a short circuit from occurring between semiconductor regions of differing conductivity types which would otherwise be caused by deviation in the location of a mask used in the photoetching step.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在单晶半导体衬底的暴露表面上形成多晶半导体层，所述衬底含有一种导电类型的杂质，并且所述多晶层为另一种导电类型的杂质;以及 在基本上防止其中包含的杂质扩散到基底中的温度下加热多晶层以使其活化。 由于杂质不会扩散，所以基板的晶体保持没有晶格缺陷。 此外，这种方法防止了在不同导电类型的半导体区域之间发生短路，否则将由光刻步骤中使用的掩模位置的偏差引起。

公开(公告)号：US4560642A

公开(公告)日：1985-12-24

申请号：US632239

申请日：1984-07-19

申请人： Toshio Yonezawa ,  Takashi Ajima ,  Shunichi Hiraki ,  Yutaka Koshino ,  Yoshitami Oka

发明人： Toshio Yonezawa ,  Takashi Ajima ,  Shunichi Hiraki ,  Yutaka Koshino ,  Yoshitami Oka

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/314 ,  B05D1/32

CPC分类号： H01L21/31144 ,  H01L21/033 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/314 ,  Y10S438/945 ,  Y10S438/95 ,  Y10S438/951

摘要： A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：选择性地施加具有规定穿孔图案的碳化硅膜作为掩模膜，以蚀刻二氧化硅膜或将杂质扩散到衬底中。

公开(公告)号：US4161743A

公开(公告)日：1979-07-17

申请号：US915541

申请日：1978-06-14

申请人： Toshio Yonezawa ,  Takashi Ajima ,  Masato Uchida

发明人： Toshio Yonezawa ,  Takashi Ajima ,  Masato Uchida

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L23/29 ,  H01L23/31 ,  H01L29/34

CPC分类号： H01L21/316 ,  H01L21/314 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L2924/0002

摘要： A semiconductor device includes a semiconductor substrate and a silicon carbide film formed in direct contact with the surface of the semiconductor substrate. The silicon carbide film may have a proper purity or include at least one element selected from the group consisting of hydrogen, oxygen, nitrogen, helium, argon or chlorine.

摘要翻译： 半导体器件包括与半导体衬底的表面直接接触形成的半导体衬底和碳化硅膜。 碳化硅膜可以具有适当的纯度或者包括选自氢，氧，氮，氦，氩或氯中的至少一种元素。

公开(公告)号：US4479830A

公开(公告)日：1984-10-30

申请号：US462201

申请日：1983-01-31

申请人： Yutaka Koshino ,  Jiro Ohshima ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Yutaka Koshino ,  Jiro Ohshima ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/2652 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A method for manufacturing a semiconductor device is shown which includes a step of ion implanting an impurity into an impurity-region formation region of a semiconductor substrate. Before or after the ion implantation step, silicon ions are implanted in a dose of 1.times.10.sup.13 to 1.times.10.sup.15 /cm.sup.2 into the impurity-region formation region and then the silicon ions so implanted are subjected to an activation treatment to form an epitaxial grown protrusion on the surface of the substrate. The protrusion is used as an alignment mark in the subsequent mask alignment step for photolithography.

摘要翻译： 示出了制造半导体器件的方法，其包括将杂质离子注入到半导体衬底的杂质区形成区域中的步骤。 在离子注入步骤之前或之后，将硅离子以1×10 13至1×10 15 / cm 2的剂量注入杂质区形成区域，然后将如此注入的硅离子进行活化处理，以在表面上形成外延生长突起 的基底。 在随后的用于光刻的掩模对准步骤中，该突起用作对准标记。