公开(公告)号：US20130278372A1

公开(公告)日：2013-10-24

申请号：US13452075

申请日：2012-04-20

申请人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Werner Robl

发明人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Werner Robl

IPC分类号： H01F5/00

CPC分类号： H01L28/10 ,  H01F27/2804 ,  H01F2017/0086 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.

摘要翻译： 半导体部件集成了无芯变压器与第一连接触点，第二连接触点，导电螺旋第一线圈，导电第一环和导电第二环。 导电螺旋第一线圈电连接在第一连接触点和第二连接触点之间。 导电的第一环围绕第一线圈和第一连接触点和第二连接触点中的一个或两个。 导电的第二环被布置在第一线圈和第一环之间，电连接到第一线圈，并且包围第一线圈以及第一连接触点和第二连接触点中的一个或两者。

公开(公告)号：US08665054B2

公开(公告)日：2014-03-04

申请号：US13452075

申请日：2012-04-20

申请人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Werner Robl

发明人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Werner Robl

IPC分类号： H01F5/00 ,  H01L27/08

CPC分类号： H01L28/10 ,  H01F27/2804 ,  H01F2017/0086 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component has integrated a coreless transformer with a first connection contact, a second connection contact, an electrically conductive spiral first coil, an electrically conductive first ring, and an electrically conductive second ring. The electrically conductive spiral first coil is electrically connected between the first connection contact and the second connection contact. The electrically conductive first ring surrounds the first coil and one or both of the first connection contact and the second connection contact. The electrically conductive second ring is arranged between the first coil and the first ring, electrically connected to the first coil, and surrounds the first coil and one or both of the first connection contact and the second connection contact.

摘要翻译： 半导体部件集成了无芯变压器与第一连接触点，第二连接触点，导电螺旋第一线圈，导电第一环和导电第二环。 导电螺旋第一线圈电连接在第一连接触点和第二连接触点之间。 导电的第一环围绕第一线圈和第一连接触点和第二连接触点中的一个或两个。 导电的第二环被布置在第一线圈和第一环之间，电连接到第一线圈，并且包围第一线圈以及第一连接触点和第二连接触点中的一个或两者。

公开(公告)号：US09214424B2

公开(公告)日：2015-12-15

申请号：US13452044

申请日：2012-04-20

申请人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gisslbl

发明人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gisslbl

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L23/522 ,  H01L21/311 ,  H01L21/322 ,  H01L21/74 ,  H01L21/3115 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/322 ,  H01L21/44 ,  H01L21/743 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

摘要翻译： 公开了一种用于制造半导体部件的圆形导线的方法。 在该方法中，提供部分完成的半导体部件。 部分完成的半导体部件具有在垂直方向上与底侧间隔开的底侧和顶侧。 还提供了一种蚀刻剂。 在顶侧设置介电层。 介电层具有至少两个不同的区域，当蚀刻剂用蚀刻剂蚀刻时，其表现出不同的蚀刻速率。 随后，在电介质层中形成沟槽，使得沟槽与不同区域中的每一个相交。 然后，通过用不同蚀刻速率的蚀刻剂蚀刻沟槽来加宽沟槽。 通过用导电材料填充加宽的沟槽，形成导体线。

公开(公告)号：US20130280879A1

公开(公告)日：2013-10-24

申请号：US13452044

申请日：2012-04-20

申请人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gissibl

发明人： Matthias Stecher ,  Markus Menath ,  Andreas Zankl ,  Anja Gissibl

IPC分类号： H01L21/02

CPC分类号： H01L21/76804 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/322 ,  H01L21/44 ,  H01L21/743 ,  H01L21/76802 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

摘要翻译： 公开了一种用于制造半导体部件的圆形导线的方法。 在该方法中，提供部分完成的半导体部件。 部分完成的半导体部件具有在垂直方向上与底侧间隔开的底侧和顶侧。 还提供了一种蚀刻剂。 在顶侧设置介电层。 介电层具有至少两个不同的区域，当蚀刻剂用蚀刻剂蚀刻时，其表现出不同的蚀刻速率。 随后，在电介质层中形成沟槽，使得沟槽与不同区域中的每一个相交。 然后，通过用不同蚀刻速率的蚀刻剂蚀刻沟槽来加宽沟槽。 通过用导电材料填充加宽的沟槽，形成导体线。

公开(公告)号：US20140070376A1

公开(公告)日：2014-03-13

申请号：US13609306

申请日：2012-09-11

申请人： Reinhard Hess ,  Katharina Umminger ,  Gabriel Maier ,  Markus Menath ,  Gunther Mackh ,  Hannes Eder ,  Alexander Heinrich

发明人： Reinhard Hess ,  Katharina Umminger ,  Gabriel Maier ,  Markus Menath ,  Gunther Mackh ,  Hannes Eder ,  Alexander Heinrich

IPC分类号： H01L21/768 ,  H01L29/02

CPC分类号： H01L23/3171 ,  H01L21/02107 ,  H01L21/30655 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/485 ,  H01L24/05 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05548 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

摘要： A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

摘要翻译： 提供了一种制造芯片布置的方法，该方法包括：在载体中形成一个孔，该载体包括至少一个芯片，其中在载体中形成孔包括：选择性地去除载体材料，从而在载体中形成空腔，形成钝化 通过选择性去除载体材料暴露的一个或多个腔壁上的材料; 选择性地去除钝化材料的一部分和通过选择性去除钝化材料暴露的另外的载体材料，其中钝化材料的另一部分保留在至少一个空腔侧壁上; 该方法还包括随后在保留在至少一个空腔侧壁上的钝化材料的另一部分上形成层。

公开(公告)号：US20130277797A1

公开(公告)日：2013-10-24

申请号：US13452669

申请日：2012-04-20

申请人： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

发明人： Markus Menath ,  Thomas Fischer ,  Hermann Wendt

IPC分类号： H01L21/76 ,  H01L27/04

CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01F17/02 ,  H01F41/042 ,  H01L21/0274 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/64 ,  H01L27/08 ,  H01L2224/48095 ,  H01L2224/48137 ,  Y10T29/4902 ,  H01L2924/00014

摘要： A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

公开(公告)号：US20140065768A1

公开(公告)日：2014-03-06

申请号：US13602219

申请日：2012-09-03

申请人： Markus Menath

发明人： Markus Menath

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

摘要： In various embodiments, a method for processing a wafer may include: providing a wafer having at least one die region and at least one metallization disposed over the at least one die region; covering the at least one metallization with a protecting layer; plasma etching the wafer to form at least one die.

摘要翻译： 在各种实施例中，用于处理晶片的方法可以包括：提供具有至少一个管芯区域和设置在所述至少一个管芯区域上的至少一个金属化的晶片; 用保护层覆盖所述至少一个金属化层; 等离子体蚀刻晶片以形成至少一个管芯。

公开(公告)号：US20120119389A1

公开(公告)日：2012-05-17

申请号：US12946138

申请日：2010-11-15

申请人： Markus Menath ,  Hermann Wendt ,  Berthold Schuderer

发明人： Markus Menath ,  Hermann Wendt ,  Berthold Schuderer

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.

摘要翻译： 一种方法包括构造半导体衬底以产生数量的半导体芯片。 每个半导体芯片包括第一主面和多个侧面。 在第一主面和侧面之间的过渡处形成有凹陷。

公开(公告)号：US08637967B2

公开(公告)日：2014-01-28

申请号：US12946138

申请日：2010-11-15

申请人： Markus Menath ,  Hermann Wendt ,  Berthold Schuderer

发明人： Markus Menath ,  Hermann Wendt ,  Berthold Schuderer

IPC分类号： H01L23/06

CPC分类号： H01L23/3114 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method includes structuring a semiconductor substrate to produce a number semiconductor chips. Each of the semiconductor chips includes a first main face and a number of side faces. An indentation is formed at a transition between the first main face and the side faces.

摘要翻译： 一种方法包括构造半导体衬底以产生数量的半导体芯片。 每个半导体芯片包括第一主面和多个侧面。 在第一主面和侧面之间的过渡处形成有凹陷。

公开(公告)号：US07289231B2

公开(公告)日：2007-10-30

申请号：US10744067

申请日：2003-12-24

申请人： Tarek Lutz ,  Markus Menath

发明人： Tarek Lutz ,  Markus Menath

IPC分类号： G01B11/14 ,  G01B11/16 ,  G01N21/00 ,  G01N21/86 ,  G01V8/00 ,  G06K9/00

CPC分类号： G03F1/84 ,  G01N21/958

摘要： An apparatus for determining physical properties of a mask blank. The apparatus includes, for example, an illumination device for radiating a predetermined light laterally into the mask blank, a detection device opposite the illumination device for detecting the light which has been scattered and/or runs through the mask blank, and an evaluation device for determining predetermined properties of the mask blank from the light which has been scattered and/or has run through the mask blank and has been detected in the detection device. The present invention likewise provides a method for determining physical properties of a mask blank.

摘要翻译： 一种用于确定面罩坯料的物理特性的装置。 该装置包括例如用于将预定光横向辐射到掩模坯料中的照明装置，与照明装置相对的用于检测已经散射和/或穿过掩模板的光的检测装置，以及用于 从已经散布和/或已经穿过掩模板的光已经在检测装置中检测到的光中确定掩模坯料的预定特性。 本发明同样提供了一种用于确定掩模坯料的物理性质的方法。