公开(公告)号：US20090184409A1

公开(公告)日：2009-07-23

申请号：US12357895

申请日：2009-01-22

申请人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

发明人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

IPC分类号： H01L23/02 ,  H01L25/10 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

公开(公告)号：US08372693B2

公开(公告)日：2013-02-12

申请号：US13538654

申请日：2012-06-29

申请人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

发明人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

IPC分类号： H01L23/02 ,  H01L23/485 ,  H01L25/10

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

公开(公告)号：US08237251B2

公开(公告)日：2012-08-07

申请号：US12357895

申请日：2009-01-22

申请人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

发明人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

IPC分类号： H01L23/02 ,  H01L23/485 ,  H01L25/10

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

公开(公告)号：US20100295162A1

公开(公告)日：2010-11-25

申请号：US12662850

申请日：2010-05-06

申请人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Dai Sasaki

发明人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Dai Sasaki

IPC分类号： H01L23/495

CPC分类号： H01L23/4985 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/50 ,  H01L24/86 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/15311

摘要： Portions of a wiring layer extending like cantilevers from an inner peripheral edge of an opening in a substrate are joined to respective terminals of a semiconductor chip mounted on the substrate. A junction portion between each portion of the wiring layer and the corresponding terminal is sealed with resin.

摘要翻译： 从衬底中的开口的内周边缘向悬臂延伸的布线层的部分接合到安装在基板上的半导体芯片的各个端子。 布线层的每个部分和相应的端子之间的接合部分用树脂密封。

公开(公告)号：US20050230829A1

公开(公告)日：2005-10-20

申请号：US11081658

申请日：2005-03-17

申请人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

发明人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

IPC分类号： H05K1/02 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H05K1/11 ,  H05K3/34

CPC分类号： H05K1/111 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09281 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on the package substrate 5. At least one of the lands 8 that make up columns that are located closest to each of the main sides that make up the outer edges of the semiconductor package has an interconnection 9 that extends from the land 8 along the surface of the package substrate. The interconnection 9 is formed such that the part that contacts the land 8 is located closer to a line that passes through the center of the land 8 and that is orthogonal to a line that connects the center of the land 8 with the center of the semiconductor package 2 than to the line that connects the center of the land 8 with the center of the semiconductor package 2.

摘要翻译： 半导体器件设置有半导体封装2和封装衬底5，封装衬底5具有通过焊料凸点4电连接到半导体封装2的焊盘8。 在封装基板5上形成有多个列，其中布置有多个焊盘8。 构成最靠近构成半导体封装的外边缘的每个主侧的列的焊盘8中的至少一个具有从焊盘8沿着封装基板的表面延伸的互连9。 互连9形成为使得接触焊盘8的部分更靠近通过焊盘8的中心的线并且与连接焊盘8的中心与半导体的中心的线垂直的线 封装2，而不是将焊盘8的中心与半导体封装2的中心连接的线。

公开(公告)号：US20050230824A1

公开(公告)日：2005-10-20

申请号：US11105546

申请日：2005-04-14

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

公开(公告)号：US20050189639A1

公开(公告)日：2005-09-01

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US20090140412A1

公开(公告)日：2009-06-04

申请号：US12363166

申请日：2009-01-30

申请人： Mitsuaki Katagiri ,  Hisashi Tanie

发明人： Mitsuaki Katagiri ,  Hisashi Tanie

IPC分类号： H01L23/49

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/3011

摘要： A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer.

摘要翻译： 通过插入弹性体将半导体芯片安装在柔性布线板上。 柔性布线板由布线固定的胶带组成。 布线的一部分突出超过带的边缘，沿着弹性体的厚度方向延伸并连接到半导体芯片的电极。 布线超过其的投影边缘突出超过弹性体边缘的长度不小于弹性体的厚度。

公开(公告)号：US07504734B2

公开(公告)日：2009-03-17

申请号：US11063877

申请日：2005-02-24

申请人： Mitsuaki Katagiri ,  Hisashi Tanie

发明人： Mitsuaki Katagiri ,  Hisashi Tanie

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/3011

摘要： A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer.

摘要翻译： 通过插入弹性体将半导体芯片安装在柔性布线板上。 柔性布线板由布线固定的胶带组成。 布线的一部分突出超过带的边缘，沿着弹性体的厚度方向延伸并连接到半导体芯片的电极。 布线超过其的投影边缘突出超过弹性体边缘的长度不小于弹性体的厚度。

公开(公告)号：US08164186B2

公开(公告)日：2012-04-24

申请号：US11105546

申请日：2005-04-14

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。