公开(公告)号：US20050230824A1

公开(公告)日：2005-10-20

申请号：US11105546

申请日：2005-04-14

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

公开(公告)号：US08164186B2

公开(公告)日：2012-04-24

申请号：US11105546

申请日：2005-04-14

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

公开(公告)号：US20100295179A1

公开(公告)日：2010-11-25

申请号：US12846120

申请日：2010-07-29

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/498

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

摘要翻译： BGA半导体器件包括半导体封装和安装在其上的半导体封装的安装板，其中半导体封装的信号电极阵列和安装板的信号电极阵列通过信号凸块耦合在一起。 BGA半导体器件还包括虚拟凸块，其加强了BGA半导体器件的弯曲强度，并被由热膨胀引起的剪切力破坏以减轻信号凸块的应力。

公开(公告)号：US08222737B2

公开(公告)日：2012-07-17

申请号：US12846120

申请日：2010-07-29

申请人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

发明人： Yuji Watanabe ,  Hisashi Tanie ,  Koji Hosokawa ,  Mitsuaki Katagiri ,  Ichiro Anjo

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/3128 ,  H01L24/81 ,  H01L2224/81801 ,  H01L2924/15311 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/09781 ,  H05K2201/2036 ,  Y02P70/613

摘要： A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

公开(公告)号：US07119428B2

公开(公告)日：2006-10-10

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjo ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L23/22 ,  H01L23/053 ,  H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US20050230829A1

公开(公告)日：2005-10-20

申请号：US11081658

申请日：2005-03-17

申请人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

发明人： Yuji Watanabe ,  Mitsuaki Katagiri ,  Hisashi Tanie ,  Atsushi Nakamura ,  Tomohiko Sato

IPC分类号： H05K1/02 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H05K1/11 ,  H05K3/34

CPC分类号： H05K1/111 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/09281 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on the package substrate 5. At least one of the lands 8 that make up columns that are located closest to each of the main sides that make up the outer edges of the semiconductor package has an interconnection 9 that extends from the land 8 along the surface of the package substrate. The interconnection 9 is formed such that the part that contacts the land 8 is located closer to a line that passes through the center of the land 8 and that is orthogonal to a line that connects the center of the land 8 with the center of the semiconductor package 2 than to the line that connects the center of the land 8 with the center of the semiconductor package 2.

摘要翻译： 半导体器件设置有半导体封装2和封装衬底5，封装衬底5具有通过焊料凸点4电连接到半导体封装2的焊盘8。 在封装基板5上形成有多个列，其中布置有多个焊盘8。 构成最靠近构成半导体封装的外边缘的每个主侧的列的焊盘8中的至少一个具有从焊盘8沿着封装基板的表面延伸的互连9。 互连9形成为使得接触焊盘8的部分更靠近通过焊盘8的中心的线并且与连接焊盘8的中心与半导体的中心的线垂直的线 封装2，而不是将焊盘8的中心与半导体封装2的中心连接的线。

公开(公告)号：US20050189639A1

公开(公告)日：2005-09-01

申请号：US11025634

申请日：2004-12-28

申请人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

发明人： Hisashi Tanie ,  Nae Hisano ,  Hiroyuki Ohta ,  Hiroaki Ikeda ,  Ichiro Anjoh ,  Mitsuaki Katagiri ,  Yuji Watanabe

IPC分类号： H01L25/18 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L25/10

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/48 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.

摘要翻译： 提供一种能够在其操作期间降低温度升高的半导体器件。 在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数 的多个半导体元件。

公开(公告)号：US07659623B2

公开(公告)日：2010-02-09

申请号：US11815084

申请日：2006-04-07

申请人： Yuji Watanabe ,  Koji Hosokawa ,  Hisashi Tanie

发明人： Yuji Watanabe ,  Koji Hosokawa ,  Hisashi Tanie

IPC分类号： H01L23/488 ,  H01L23/48 ,  H01L25/07 ,  H01L23/12 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00

摘要： An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.

摘要翻译： 提供了能够防止表层布线的应力集中区域的布线断裂的半导体装置等电子部件。 在设置有支撑球（5）的半导体装置中，在支撑球（5）附近的区域（7（A））和末端的区域（7（B））中不形成普通的布线 的面向支撑球（5）的半导体芯片，其是封装衬底（2）的应力集中区域。 相反，布线（6（C））远离这些区域形成，或者在这些区域中形成宽布线。

公开(公告)号：US20080150115A1

公开(公告)日：2008-06-26

申请号：US11815084

申请日：2006-04-07

申请人： Yuji Watanabe ,  Koji Hosokawa ,  Hisashi Tanie

发明人： Yuji Watanabe ,  Koji Hosokawa ,  Hisashi Tanie

IPC分类号： H01L23/488

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/3511 ,  H01L2924/00

摘要： An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.

摘要翻译： 提供了能够防止表层布线的应力集中区域的布线断裂的半导体装置等电子部件。 在设置有支撑球（5）的半导体装置中，在支撑球（5）附近的区域（7（A））和末端的区域（7（B））中不形成普通的布线 的面向支撑球（5）的半导体芯片，其是封装衬底（2）的应力集中区域。 相反，布线（6（C））远离这些区域形成，或者在这些区域中形成宽布线。

公开(公告)号：US20090184409A1

公开(公告)日：2009-07-23

申请号：US12357895

申请日：2009-01-22

申请人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

发明人： Mitsuaki KATAGIRI ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

IPC分类号： H01L23/02 ,  H01L25/10 ,  H01L23/48 ,  H01L23/485

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。