公开(公告)号：US08431459B2

公开(公告)日：2013-04-30

申请号：US12934233

申请日：2009-03-26

申请人： Mitsuru Takenaka ,  Shinichi Takagi ,  Masahiko Hata ,  Osamu Ichikawa

发明人： Mitsuru Takenaka ,  Shinichi Takagi ,  Masahiko Hata ,  Osamu Ichikawa

IPC分类号： H01L21/00

CPC分类号： H01L29/7787 ,  H01L21/28264 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78648 ,  H01L29/78681

摘要： It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.

摘要翻译： 本发明的目的是使用实用和简单的方法在氧化物层和3-5族化合物半导体之间形成良好的界面。 提供了包括第一半导体层的半导体晶片，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 和形成为与第一半导体层接触的第二半导体层是与InP晶格匹配或伪晶格匹配的组3-5化合物半导体层，并且可相对于第一半导体层选择性地氧化。 还提供了一种半导体器件，其包括第一半导体层，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 通过相对于第一半导体层选择性地氧化形成为与第一半导体层接触的组3-5化合物的第二半导体层的至少一部分，并且晶格匹配或伪晶格匹配的InP形成的氧化物层 ; 以及将电场与形成在第一半导体层中的沟道相加的控制电极。

公开(公告)号：US20110018033A1

公开(公告)日：2011-01-27

申请号：US12934233

申请日：2009-03-26

申请人： Mitsuru Takenaka ,  Shinichi Takagi ,  Masahiko Hata ,  Osamu Ichikawa

发明人： Mitsuru Takenaka ,  Shinichi Takagi ,  Masahiko Hata ,  Osamu Ichikawa

IPC分类号： H01L29/205 ,  H01L21/283 ,  H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/7787 ,  H01L21/28264 ,  H01L29/205 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/78648 ,  H01L29/78681

摘要： It is an objective of the present invention to form a favorable interface between an oxide layer and a group 3-5 compound semiconductor using a practical and simple method.Provided is a semiconductor wafer comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; and a second semiconductor layer that is formed to contact the first semiconductor layer, is a group 3-5 compound semiconductor layer that lattice matches or pseudo-lattice matches with InP, and can be selectively oxidized relative to the first semiconductor layer. Also provided is a semiconductor device comprising a first semiconductor layer that is a group 3-5 compound not containing arsenic and that lattice matches or pseudo-lattice matches with InP; an oxide layer formed by selectively oxidizing, relative to the first semiconductor layer, at least a portion of a second semiconductor layer that is a group 3-5 compound formed to contact the first semiconductor layer and that lattice matches or pseudo-lattice matches with InP; and a control electrode that adds an electric field to a channel formed in the first semiconductor layer.

摘要翻译： 本发明的目的是使用实用和简单的方法在氧化物层和3-5族化合物半导体之间形成良好的界面。 提供了包括第一半导体层的半导体晶片，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 和形成为与第一半导体层接触的第二半导体层是与InP晶格匹配或伪晶格匹配的组3-5化合物半导体层，并且可相对于第一半导体层选择性地氧化。 还提供了一种半导体器件，其包括第一半导体层，其是不含砷的组3-5化合物，并且晶格匹配或伪晶格与InP匹配; 通过相对于第一半导体层选择性地氧化形成为与第一半导体层接触的组3-5化合物的第二半导体层的至少一部分，并且晶格匹配或伪晶格匹配的InP形成的氧化物层 ; 以及将电场与形成在第一半导体层中的沟道相加的控制电极。

公开(公告)号：US20110233689A1

公开(公告)日：2011-09-29

申请号：US13133092

申请日：2009-11-27

申请人： Masahiko Hata ,  Noboru Fukuhara ,  Hisashi Yamada ,  Shinichi Takagi ,  Masakazu Sugiyama ,  Mitsuru Takenaka ,  Tetsuji Yasuda ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii ,  Akihiro Ohtake ,  Jun Nara

发明人： Masahiko Hata ,  Noboru Fukuhara ,  Hisashi Yamada ,  Shinichi Takagi ,  Masakazu Sugiyama ,  Mitsuru Takenaka ,  Tetsuji Yasuda ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii ,  Akihiro Ohtake ,  Jun Nara

IPC分类号： H01L29/78 ,  H01L29/04 ,  H01L21/336 ,  H01L29/20 ,  H01L21/20

CPC分类号： H01L29/045 ,  H01L29/20 ,  H01L29/7833 ,  H01L29/78681

摘要： There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.

摘要翻译： 提供了一种半导体器件，其包括具有锌闪光体型晶体结构的III-V族化合物半导体，与III-V族化合物半导体的（111）面接触的绝缘材料， 相当于（111）面的III-V族化合物半导体，或相对于（111）面或与（111）面相当的面的偏角的平面，和与MIS接触的MIS型电极 具有绝缘材料并且包括金属导电材料。

公开(公告)号：US09112035B2

公开(公告)日：2015-08-18

申请号：US13410872

申请日：2012-03-02

申请人： Hisashi Yamada ,  Masahiko Hata ,  Masafumi Yokoyama ,  Mitsuru Takenaka ,  Shinichi Takagi ,  Tetsuji Yasuda ,  Hideki Takagi ,  Yuji Urabe

发明人： Hisashi Yamada ,  Masahiko Hata ,  Masafumi Yokoyama ,  Mitsuru Takenaka ,  Shinichi Takagi ,  Tetsuji Yasuda ,  Hideki Takagi ,  Yuji Urabe

IPC分类号： H01L29/02 ,  H01L29/786 ,  H01L21/762 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L29/78681 ,  H01L21/76251 ,  H01L21/76256 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66742

摘要： A semiconductor substrate includes a substrate, an insulating layer, and a semiconductor layer. The insulating layer is over and in contact with the substrate. The insulating layer includes at least one of an amorphous metal oxide and an amorphous metal nitride. The semiconductor layer is over and in contact with the insulating layer. The semiconductor layer is formed by crystal growth.

摘要翻译： 半导体衬底包括衬底，绝缘层和半导体层。 绝缘层在衬底上并与衬底接触。 绝缘层包括无定形金属氧化物和无定形金属氮化物中的至少一种。 半导体层在绝缘层上方并与之接触。 半导体层通过晶体生长形成。

公开(公告)号：US08779471B2

公开(公告)日：2014-07-15

申请号：US13413216

申请日：2012-03-06

申请人： Masahiko Hata ,  Hisashi Yamada ,  Noboru Fukuhara ,  Shinichi Takagi ,  Mitsuru Takenaka ,  Masafumi Yokoyama ,  Tetsuji Yasuda ,  Yuji Urabe ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii

发明人： Masahiko Hata ,  Hisashi Yamada ,  Noboru Fukuhara ,  Shinichi Takagi ,  Mitsuru Takenaka ,  Masafumi Yokoyama ,  Tetsuji Yasuda ,  Yuji Urabe ,  Noriyuki Miyata ,  Taro Itatani ,  Hiroyuki Ishii

IPC分类号： H01L29/66

CPC分类号： H01L29/7786 ,  H01L21/26553 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66318 ,  H01L29/66522

摘要： Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of Inx1Ga1-x1Asy1P1-y1 (0

摘要翻译： 提供了一种场效应晶体管，其包括栅极绝缘层，与栅极绝缘层接触的第一半导体晶体层和第二半导体晶体层与第一半导体晶体层的晶格匹配或伪晶格匹配。 这里，栅绝缘层，第一半导体晶体层和第二半导体晶体层按栅极绝缘层，第一半导体晶体层和第二半导体晶体层的顺序排列，第一半导体晶体层被制成 的In x Ga 1-x As y 1 P 1-y 1（0

公开(公告)号：US20110012178A1

公开(公告)日：2011-01-20

申请号：US12934474

申请日：2009-03-26

申请人： Masakazu Sugiyama ,  Yukihiro Shimogaki ,  Masahiko Hata ,  Osamu Ichikawa

发明人： Masakazu Sugiyama ,  Yukihiro Shimogaki ,  Masahiko Hata ,  Osamu Ichikawa

IPC分类号： H01L29/20 ,  H01L21/20 ,  H01L29/78

CPC分类号： H01L29/51 ,  H01L21/28264 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/94

摘要： Provided is a semiconductor wafer having decreased interface state density at the semiconductor-insulator interface, a method of manufacturing this semiconductor wafer, and a semiconductor device.Provided is a semiconductor wafer comprising a group 3-5 compound semiconductor layer containing arsenic; and an insulating layer that is an oxide, a nitride, or an oxynitride, wherein arsenic oxides are not detected between the semiconductor layer and the insulating layer. This semiconductor wafer may be such that, when using X-ray photoelectron spectroscopy to observe photoelectron intensity of an element existing between the semiconductor layer and the insulating layer, an oxide peak caused by oxidized arsenic is not detected on a higher bonding energy side of an element peak caused by the arsenic.

摘要翻译： 提供了一种在半导体 - 绝缘体界面处具有降低的界面态密度的半导体晶片，该半导体晶片的制造方法以及半导体器件。 提供了包含含有砷的组3-5化合物半导体层的半导体晶片; 以及绝缘层，其是氧化物，氮化物或氧氮化物，其中在半导体层和绝缘层之间未检测到砷氧化物。 该半导体晶片可以使得当使用X射线光电子能谱观察存在于半导体层和绝缘层之间的元素的光电子强度时，在氧化砷引起的氧化物峰不能在 元素峰由砷引起。

公开(公告)号：US08890213B2

公开(公告)日：2014-11-18

申请号：US13301272

申请日：2011-11-21

申请人： Sadanori Yamanaka ,  Masahiko Hata ,  Noboru Fukuhara

发明人： Sadanori Yamanaka ,  Masahiko Hata ,  Noboru Fukuhara

IPC分类号： H01L29/70 ,  H01L29/66 ,  H01L31/0304 ,  H01L29/737 ,  H01L21/02 ,  H01L31/0312 ,  H01L31/18

CPC分类号： H01L29/7371 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66318 ,  H01L31/0304 ,  H01L31/03044 ,  H01L31/0312 ,  H01L31/1852 ,  Y02E10/544 ,  Y02P70/521

摘要： There is provided a semiconductor wafer including a base wafer that has an impurity region in which an impurity atom has been introduced into silicon, a plurality of seed bodies provided in contact with the impurity region, and a plurality of compound semiconductors each provided in contact with the corresponding seed bodies and lattice-matched or pseudo-lattice-matched to the corresponding seed bodies. The semiconductor wafer can further include an inhibitor provided on the base wafer and in which a plurality of apertures exposing at least a part of the impurity region are provided.

摘要翻译： 提供了一种半导体晶片，其包括：基底晶片，其具有将杂质原子引入到硅中的杂质区域，与杂质区域接触的多个晶种;以及多个化合物半导体，各自与 相应的种子体和与对应的种子晶格匹配或伪晶格匹配。 半导体晶片还可以包括设置在基底晶片上的抑制剂，其中设置暴露至少一部分杂质区域的多个孔。

公开(公告)号：US08878250B2

公开(公告)日：2014-11-04

申请号：US13594442

申请日：2012-08-24

申请人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada ,  Kazuhiko Honjo

发明人： Masahiko Hata ,  Sadanori Yamanaka ,  Tomoyuki Takada ,  Kazuhiko Honjo

IPC分类号： H01L29/737 ,  H01L23/31 ,  H01L27/06 ,  H01L23/00

CPC分类号： H01L27/0605 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/13023 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element.

摘要翻译： 提供电子器件，其包括：其表面由硅晶体制成的基底晶片; 在硅晶体的部分区域上直接或间接形成的3-5族化合物半导体晶体; 包含部分3-5族化合物半导体晶体作为活性层的电子元件; 直接或间接地形成在基底晶片上并覆盖电子元件的绝缘膜; 在绝缘膜上直接或间接形成的电极; 延伸穿过所述绝缘膜的第一耦合布线，其至少一部分直接或间接地形成在所述绝缘膜上，并且将所述电子元件与所述电极电耦合; 绝缘膜上直接或间接形成的无源元件; 延伸穿过绝缘膜的第二耦合布线，其至少一部分直接或间接地形成在绝缘膜上，并将电子元件与无源元件电连接。

公开(公告)号：US08772830B2

公开(公告)日：2014-07-08

申请号：US12811074

申请日：2008-12-26

申请人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata

发明人： Tomoyuki Takada ,  Sadanori Yamanaka ,  Masahiko Hata

IPC分类号： H01L29/12

CPC分类号： H01L29/045 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02516 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/205 ,  H01L29/66242 ,  H01L29/7371

摘要： A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; a buffer layer that is crystal-grown on the Ge layer and is a group 3-5 compound semiconductor layer containing P; and a functional layer that is crystal-grown on the buffer layer. The Ge layer may be formed then annealing with a temperature and duration that enables movement of crystal defects.

摘要翻译： 实现了具有良好热释放特性的廉价Si晶片的高质量GaAs型晶体薄膜。 提供了包括Si晶片的半导体晶片; 所述抑制层形成在所述晶片上并且抑制晶体生长，所述抑制层包括覆盖所述晶片的一部分的覆盖区域和不覆盖所述覆盖区域内的所述晶片的一部分的开放区域; 在开放区域晶体生长的Ge层; 在Ge层上晶体生长并且是含有P的3-5族化合物半导体层的缓冲层; 以及在缓冲层上晶体生长的功能层。 可以形成Ge层，然后以能够移动晶体缺陷的温度和持续时间进行退火。

公开(公告)号：US08766318B2

公开(公告)日：2014-07-01

申请号：US12920455

申请日：2009-02-27

申请人： Masahiko Hata ,  Tomoyuki Takada

发明人： Masahiko Hata ,  Tomoyuki Takada

IPC分类号： H01L29/12

CPC分类号： H01L29/16 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02551 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78648 ,  H01L29/78681

摘要： The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.

摘要翻译： 目的是提高复合半导体器件的高速切换等能力。 提供了包括硅晶片的半导体晶片; 绝缘膜，其形成在所述硅晶片上，并且具有到达所述硅晶片的开口部分; 形成在开口部的Ge晶体; 种子化合物半导体晶体，其以Ge晶体为核生长并突出超过绝缘膜的表面; 横向生长的化合物半导体层，其以种子化合物半导体晶体的指定表面作为种子表面在绝缘膜上横向生长。