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公开(公告)号：US20110104426A1
公开(公告)日：2011-05-05
申请号：US12608363
申请日：2009-10-29
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译： 介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。 介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。 介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。 此外，介电材料层密封第一和第二基板之间的界面的整个周边。 如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。
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公开(公告)号：US20120288687A1
公开(公告)日：2012-11-15
申请号：US13556369
申请日：2012-07-24
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译： 介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。 介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。 介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。 此外，介电材料层密封第一和第二基板之间的界面的整个周边。 如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。
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公开(公告)号：US08679611B2
公开(公告)日：2014-03-25
申请号：US13556369
申请日：2012-07-24
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译： 介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。 介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。 介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。 此外，介电材料层密封第一和第二基板之间的界面的整个周边。 如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。
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公开(公告)号：US08287980B2
公开(公告)日：2012-10-16
申请号：US12608363
申请日：2009-10-29
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译： 介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。 介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。 介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。 此外，介电材料层密封第一和第二基板之间的界面的整个周边。 如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。
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公开(公告)号：US08999764B2
公开(公告)日：2015-04-07
申请号：US11836819
申请日：2007-08-10
IPC分类号： H01L21/00 , H01L23/532 , H01L23/556
CPC分类号： H01L23/5329 , H01L23/556 , H01L2924/0002 , Y10S438/958 , Y10S438/967 , H01L2924/00
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。
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6.发明授权Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier 有权使用接口晶片作为永久载体制造3D集成电路器件的方法公开(公告)号：US08664081B2
公开(公告)日：2014-03-04
申请号：US13572037
申请日：2012-08-10
申请人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
发明人： Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Steven J. Koester , Fei Liu , Sampath Purushothaman , Albert M. Young , Roy R. Yu
IPC分类号： H01L21/30
CPC分类号： H01L25/0657 , H01L21/6835 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/0401 , H01L2224/05001 , H01L2224/05008 , H01L2224/05009 , H01L2224/05024 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05558 , H01L2224/05568 , H01L2224/0557 , H01L2224/056 , H01L2224/131 , H01L2224/16227 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/73153 , H01L2224/73253 , H01L2224/83121 , H01L2224/83895 , H01L2224/92242 , H01L2224/94 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/15311 , H01L2924/157 , H01L2924/37001 , H01L2224/83 , H01L2224/11 , H01L2924/014 , H01L2924/00014
摘要： A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.
摘要翻译： 提供了一种计算机可读介质，其由包括用于执行制造3D集成电路结构的方法的指令的程序编码。 提供了包括第一布线层和穿硅通孔的接口晶片，以及包括有源电路的第一有源电路层晶片。 第一有源电路层晶片被结合到界面晶片。 然后，去除第一有源电路层晶片的第一部分，使得第二部分保持附着到界面晶片。 包括接口晶片和第一有源电路层晶片的第二部分的堆叠结构被结合到基底晶片。 接下来，将界面晶片减薄以形成界面层，并且在界面层上形成通过界面层中的穿硅通孔耦合到第一布线层的金属化。
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公开(公告)号：US20130334691A1
公开(公告)日：2013-12-19
申请号：US13525823
申请日：2012-06-18
IPC分类号： H01L23/52 , H01L21/283
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.
摘要翻译： 一种形成在开口中的结构，其具有由非金属材料限定的基本上垂直的侧壁，并且具有由导电垫限定的基本上水平的底部，该结构包括覆盖侧壁的扩散阻挡层和由导电材料构成的填充物。 所述结构包括将所述扩散阻挡物与所述导电材料分离的第一金属间化合物，所述第一金属间化合物包括合金材料和所述导电材料，并且机械地结合到所述导电材料上，所述合金材料是选自以下的至少一种材料： 铬，锡，镍，镁，钴，铝，锰，钛，锆，铟，钯和银的组合; 以及位于所述扩散阻挡层和所述第一金属间化合物之间且平行于所述开口的侧壁的第一高摩擦界面，其中所述第一高摩擦界面导致所述扩散阻挡层和所述第一金属间化合物之间的机械结合。
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公开(公告)号：US08546961B2
公开(公告)日：2013-10-01
申请号：US12987202
申请日：2011-01-10
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/544 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2223/54426 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/8385 , H01L2224/83896 , H01L2224/9202 , H01L2224/94 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2224/83
摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
摘要翻译： 公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。 该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。
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公开(公告)号：US08492878B2
公开(公告)日：2013-07-23
申请号：US12840688
申请日：2010-07-21
IPC分类号： H01L29/40
CPC分类号： H01L21/76898 , H01L21/568 , H01L21/6835 , H01L23/3171 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/93 , H01L24/94 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/03002 , H01L2224/0401 , H01L2224/0557 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/11002 , H01L2224/11334 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/81801 , H01L2224/93 , H01L2224/94 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/10253 , H01L2924/12044 , H01L2924/15788 , H01L2924/014 , H01L2224/81 , H01L2224/03 , H01L2224/11 , H01L2924/00 , H01L2224/05552
摘要： A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.
摘要翻译： 提供了由于背面平坦化处理而对金属污染免疫的贯穿衬底通孔（TSV）结构。 在形成贯穿衬底通孔（TSV）沟槽之后，扩散阻挡衬里共形沉积在TSV沟槽的侧壁上。 通过在扩散阻挡衬里的垂直部分上沉积介电材料形成电介质衬垫。 通过随后填充TSV沟槽形成金属导电通孔结构。 去除扩散阻挡衬里的水平部分。 扩散阻挡衬里通过阻挡源自金属导电通路结构的残余金属材料进入衬底的半导体材料来保护衬底的半导体材料，从而保护衬底内的半导体器件免受金属污染。
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10.发明申请METHOD OF FORMING A THROUGH-SILICON VIA UTILIZING A METAL CONTACT PAD IN A BACK-END-OF-LINE WIRING LEVEL TO FILL THE THROUGH-SILICON VIA 有权通过利用金属接触垫在后端线接线层中形成穿透硅的方法来填充穿透硅公开(公告)号：US20120315753A1
公开(公告)日：2012-12-13
申请号：US13154905
申请日：2011-06-07
IPC分类号： H01L21/283
CPC分类号： H01L21/76898 , H01L21/2885 , H01L21/306 , H01L21/6835 , H01L21/76841 , H01L21/76846 , H01L21/76879 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2221/1084 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/05022 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13023 , H01L2224/131 , H01L2924/00014 , H01L2924/07802 , H01L2924/00012 , H01L2924/01074 , H01L2924/014 , H01L2924/00 , H01L2224/05552
摘要： A method for fabricating through-silicon vias (TSVs) for semiconductor devices is provided. Specifically, the method involves utilizing copper contact pads in a back-end-of-line wiring level, wherein the copper contact pads act as cathodes for performing an electroplating technique to fill TSVs with plated-conductive material (e.g., copper) from an electroplating solution. Moreover, the method provides a way to fill high aspect ratio TSVs with minimal additional semiconductor fabrication process steps, which can increase the silicon area that is available for forming additional electronic components on integrated circuits.
摘要翻译： 提供了一种用于制造用于半导体器件的硅通孔（TSV）的方法。 具体地，该方法包括在后端线路布线层中利用铜接触焊盘，其中铜接触焊盘用作执行电镀技术的阴极，用电镀导电材料（例如铜）填充TSV 解。 此外，该方法提供了通过最小的附加半导体制造工艺步骤填充高纵横比TSV的方法，其可以增加可用于在集成电路上形成附加电子部件的硅面积。
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