利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

78 条记录 (耗时 0.026 秒)

    Semiconductor device including silicon ladder resin layer
    1.
    发明授权
    Semiconductor device including silicon ladder resin layer 失效
    半导体器件包括硅梯形树脂层

    公开(公告)号：US5510653A

    公开(公告)日：1996-04-23

    申请号：US40968

    申请日：1993-03-31

    申请人： Noriaki Fujiki ,  Shigeru Harada ,  Hiroshi Adachi ,  Etsushi Adachi

    发明人： Noriaki Fujiki ,  Shigeru Harada ,  Hiroshi Adachi ,  Etsushi Adachi

    IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/56

    CPC分类号： H01L21/76819 ,  H01L23/5329 ,  H01L2924/0002

    摘要： Disclosed herein is a semiconductor device having a multilayer interconnection structure, which is provided with a plurality of via holes having constant diameters. Patterns of a first interconnection layer are provided on a semiconductor substrate. An interlayer insulating film is provided over the semiconductor substrate, to cover the patterns of the first interconnection layer. A silicon ladder resin film is applied onto the surface of the interlayer insulating film, to flatten the same. First and second via holes are provided through the silicon ladder resin film and the interlayer insulating film, to expose first and second coupling portions provided on the surfaces of the patterns of the first interconnection layer. A second interconnection layer is provided over the semiconductor substrate, to be connected with the first and second coupling portions through the first and second via holes respectively.

    摘要翻译： 本文公开了具有多层互连结构的半导体器件，其具有多个具有恒定直径的通孔。 第一互连层的图案设置在半导体衬底上。 在半导体衬底上设置层间绝缘膜，以覆盖第一互连层的图案。 将硅梯形树脂膜施加到层间绝缘膜的表面上以使其平坦化。 通过硅梯形树脂膜和层间绝缘膜提供第一和第二通孔，以露出设置在第一互连层的图案的表面上的第一和第二耦合部分。 第二互连层设置在半导体衬底上，分别通过第一和第二通孔与第一和第二耦合部分连接。

    Multilayer interconnection structure including an alignment mark
    6.
    发明授权
    Multilayer interconnection structure including an alignment mark 失效
    多层互连结构包括对准标记

    公开(公告)号：US06677682B1

    公开(公告)日：2004-01-13

    申请号：US09620555

    申请日：2000-07-20

    申请人： Noriaki Fujiki ,  Shigeru Harada ,  Takashi Yamashita

    发明人： Noriaki Fujiki ,  Shigeru Harada ,  Takashi Yamashita

    IPC分类号： H01L23544

    CPC分类号： H01L23/544 ,  H01L21/76819 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interlayer insulating film (21) is formed on a substrate (1), and a polysilicon layer (10) is formed on the interlayer insulating film (21). An interlayer insulating film (22) is formed to cover the polysilicon layer (10), and a polysilicon layer (11) is formed on the interlayer insulating film (22). An interlayer insulating film (23) is formed to cover the interlayer insulating film (22). A hole (20M) for a mark to constitute an alignment mark or the like is formed from a surface (23S) of the interlayer insulating film (23) to the polysilicon layer (11). The hole (20M) for a mark is larger than a contact hole formed from the surface (23S) to the substrate (1) but is shallower than the contact hole. Consequently, a concave portion corresponding to the hole (20M) for a mark is formed, with difficulty, on a silicon oxide layer to be subjected to CMP polishing and then become an interlayer insulting film (4). Therefore, it is possible to prevent a slurry from remaining in the concave portion. Thus, it is possible to obtain a semiconductor device having high reliability without a disadvantage such as a wiring disconnection or the like which is caused by the remaining or scattering of the slurry to be used for a CMP method.

    摘要翻译： 在基板（1）上形成层间绝缘膜（21），在层间绝缘膜（21）上形成多晶硅层（10）。 形成层间绝缘膜（22）以覆盖多晶硅层（10），并且在层间绝缘膜（22）上形成多晶硅层（11）。 形成层间绝缘膜（23）以覆盖层间绝缘膜（22）。 从层间绝缘膜（23）到多晶硅层（11）的表面（23S）形成用于构成对准标记等的标记的孔（20M）。 用于标记的孔（20M）大于从表面（23S）到基板（1）形成的接触孔，但是比接触孔浅。 因此，难以在氧化硅层上形成与用于标记的孔（20M）对应的凹部，进行CMP研磨后，成为层间绝缘膜（4）。 因此，可以防止浆料残留在凹部中。 因此，可以获得具有高可靠性的半导体器件，而没有由用于CMP方法的浆料的剩余或散射引起的诸如布线断开等的缺点。

    Interconnection structure of semiconductor integrated circuit device and manufacturing method thererfor
    7.
    发明授权
    Interconnection structure of semiconductor integrated circuit device and manufacturing method thererfor 失效
    半导体集成电路器件的互连结构及其制造方法

    公开(公告)号：US5488014A

    公开(公告)日：1996-01-30

    申请号：US213417

    申请日：1994-03-15

    申请人： Shigeru Harada ,  Junichi Arima ,  Noriaki Fujiki

    发明人： Shigeru Harada ,  Junichi Arima ,  Noriaki Fujiki

    IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L2924/0002

    摘要： A surface of a first aluminum interconnection layer in a connection hole is exposed to a plasma of oxygen or fluorine-containing gas during the forming step of the connection hole. In order to remove the thin deterioration layer which forms as a result, sputter etching is effected by an argon ion. There are residual particles of the oxide and fluoride of aluminum on the surface of the first aluminum interconnection layer. A titanium layer is formed on the insulating layer to be in contact with the surface of the first aluminum layer through the through hole. A titanium compound layer is formed on the titanium layer. A second aluminum layer is formed on the titanium compound layer. A heat treatment is effected to decompose the residual particles and to form an intermetallic compound (TiAl.sub.3).

    摘要翻译： 在连接孔的形成步骤期间，连接孔中的第一铝互连层的表面暴露于氧或含氟气体的等离子体。 为了除去形成的薄劣化层，通过氩离子进行溅射蚀刻。 在第一铝互连层的表面上存在铝的氧化物和氟化物的残留颗粒。 在绝缘层上形成钛层，以通过通孔与第一铝层的表面接触。 在钛层上形成钛化合物层。 在钛化合物层上形成第二铝层。 进行热处理以分解残余颗粒并形成金属间化合物（TiAl 3）。