公开(公告)号：US06911229B2

公开(公告)日：2005-06-28

申请号：US10215324

申请日：2002-08-09

申请人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Fenton Read McFeely ,  Milan Paunovic

发明人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Fenton Read McFeely ,  Milan Paunovic

IPC分类号： H01L21/285 ,  H01L21/288 ,  H01L21/768 ,  H01L23/532 ,  B05D5/12 ,  C23C14/32 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24322 ,  Y10T428/24917 ,  H01L2924/00

摘要： An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; a barrier layer located in the via opening; an interlayer of palladium and/or platinum on the barrier layer; and a layer of copper or copper alloy on the interlayer is provided.

摘要翻译： 一种互连结构，包括其中具有通孔开口的介电层的基板; 位于通孔开口中的阻挡层; 阻挡层上的钯和/或铂的中间层; 并且在中间层上设置一层铜或铜合金。

公开(公告)号：US06416812B1

公开(公告)日：2002-07-09

申请号：US09605871

申请日：2000-06-29

申请人： Panayotis Andricacos ,  Steven H. Boettcher ,  Fenton Read McFeely ,  Milan Paunovic

发明人： Panayotis Andricacos ,  Steven H. Boettcher ,  Fenton Read McFeely ,  Milan Paunovic

IPC分类号： B05D512

CPC分类号： H01L21/76871 ,  C23C18/405 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879

摘要： Copper is deposited onto a barrier layer such as tungsten from an electroless copper plating bath having a pH of at least 12.89 and a deposition rate of 50 nanometers/minute or less.

摘要翻译： 铜从pH为至少12.89，沉积速率为50纳米/分钟以下的化学镀铜浴沉积到诸如钨的阻挡层上。

公开(公告)号：US07227265B2

公开(公告)日：2007-06-05

申请号：US10810719

申请日：2004-03-29

申请人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

发明人： Panayotis C. Andricacos ,  Steven H. Boettcher ,  Dean S. Chung ,  Hariklia Deligianni ,  James E. Fluegel ,  Wilma Jean Horkans ,  Keith T. Kwietniak ,  Peter S. Locke ,  Christopher C. Parks ,  Soon-Cheon Seo ,  Andrew H. Simon ,  Erick G. Walton

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D3/38 ,  C25D5/024 ,  C25D5/18 ,  C25D7/123 ,  H01L21/76877

摘要： Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 μm and via openings filled with electroplated copper than is substantially free of internal seams or voids.

摘要翻译： 使用包含溶解的铜盐的电镀铜浴获得至少基本上不含内部接缝或空隙的铜导体的互连结构，其中盐的浓度为酸的至少约0.4摩尔浓度至高达约0.5摩尔浓度。 还提供了具有大于约3的宽高比和小于约0.275μm的宽度的铜镶嵌结构以及填充有电镀铜的通孔，基本上不含内部接缝或空隙。

公开(公告)号：US20080237053A1

公开(公告)日：2008-10-02

申请号：US12127477

申请日：2008-05-27

申请人： Panayotis Andricacos ,  Steven H. Boettcher ,  Sandra G. Malhotra ,  Milan Paunovic ,  Craig Ransom

发明人： Panayotis Andricacos ,  Steven H. Boettcher ,  Sandra G. Malhotra ,  Milan Paunovic ,  Craig Ransom

IPC分类号： C25D5/34

CPC分类号： C25D3/562 ,  C25D7/12 ,  H01L21/2885 ,  H01L21/76846

摘要： An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; wherein the opening has an underlayer of cobalt and/or nickel therein, barrier layer of an alloy of cobalt and/or nickel; and tungsten is provided.

摘要翻译： 一种互连结构，包括其中具有通孔开口的介电层的基板; 其中所述开口具有其中的钴和/或镍的底层，钴和/或镍的合金的阻挡层; 并提供钨。

公开(公告)号：US06572982B1

公开(公告)日：2003-06-03

申请号：US09604539

申请日：2000-06-27

申请人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

发明人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

IPC分类号： B32B1504

CPC分类号： C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/76877 ,  Y10T428/12535 ,  Y10T428/12646 ,  Y10T428/1291

摘要： An electromigration-resistant copper film structure and the process for forming the structure. The film structure contains a high impurity content, is resistant to grain growth, and possesses superior metallurgical, thermo-mechanical, and electrical properties. The process comprises the steps of: (a) providing a seed layer at least indirectly on a substrate, the seed layer having an exposed surface; (b) immersing the substrate in a plating solution; (c) electrodepositing a copper-containing film on the exposed surface of the seed layer, the copper-containing film having a first surface; (d) maintaining the substrate in an immersed state within the plating solution; (e) electrodepositing a further copper-containing film from the plating solution onto the first surface; (f) removing the substrate from the plating solution; and (g) drying the substrate.

摘要翻译： 一种抗电镀铜膜结构和形成该结构的方法。 膜结构含有高杂质含量，耐晶粒生长，具有优良的冶金，热机械和电学性能。 该方法包括以下步骤：（a）至少间接地在基底上提供种子层，籽晶层具有暴露表面; （b）将基板浸入电镀液中; （c）在种子层的暴露表面上电沉积含铜膜，所述含铜膜具有第一表面; （d）将所述基板保持在所述电镀液中的浸渍状态; （e）将另外的含铜膜从所述电镀溶液电沉积到所述第一表面上; （f）从电镀液中除去基板; 和（g）干燥基材。

公开(公告)号：US20080156987A1

公开(公告)日：2008-07-03

申请号：US11617386

申请日：2006-12-28

申请人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun Yu Wang

发明人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun Yu Wang

IPC分类号： G01N23/04

CPC分类号： G01N1/2806

摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. TEOS oxide marker is readily visible during the polish, has a similar polish rate as semiconductor material, and reduces contamination during the sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并且减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。

公开(公告)号：US06383929B1

公开(公告)日：2002-05-07

申请号：US09759015

申请日：2001-01-11

申请人： Steven H. Boettcher ,  Herbert L. Ho ,  Mark Hoinkis ,  Hyun Koo Lee ,  Yun-Yu Wang ,  Kwong Hon Wong

发明人： Steven H. Boettcher ,  Herbert L. Ho ,  Mark Hoinkis ,  Hyun Koo Lee ,  Yun-Yu Wang ,  Kwong Hon Wong

IPC分类号： H01L2144

CPC分类号： H01L21/76846 ,  H01L21/76858 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In integrated circuits having copper interconnect and low-k interlayer dielectrics, a problem of open circuits after heat treatment was discovered and solved by the use of a first liner layer of Ti, followed by a conformal liner layer of CVD TiN, followed in turn by a final liner layer of Ta or TaN, thus improving adhesion between the via and the underlying copper layer while reducing the increase in resistance caused by alloying between the Ti and the Copper to an acceptable amount.

摘要翻译： 在具有铜互连和低k层间电介质的集成电路中，通过使用第一内衬层Ti，随后是CVD TiN的共形内衬层，然后依次由 Ta或TaN的最终衬垫层，从而改善了通孔和下面的铜层之间的粘附性，同时将Ti和铜之间的合金化引起的电阻增加减少到可接受的量。

公开(公告)号：US6123825A

公开(公告)日：2000-09-26

申请号：US203926

申请日：1998-12-02

申请人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

发明人： Cyprian E. Uzoh ,  Steven H. Boettcher ,  Patrick W. DeHaven ,  Christopher C. Parks ,  Andrew H. Simon

IPC分类号： H01L21/3205 ,  C25D5/10 ,  C25D7/00 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  C23C28/00 ,  C23C28/02 ,  C25D5/02 ,  C25D5/34 ,  C25D5/50

CPC分类号： C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/76877 ,  Y10T428/12535 ,  Y10T428/12646 ,  Y10T428/1291

摘要： An electromigration-resistant copper film structure and the process for forming the structure. The film structure contains a high impurity content, is resistant to grain growth, and possesses superior metallurgical, thermo-mechanical, and electrical properties. The process comprises the steps of: (a) providing a seed layer at least indirectly on a substrate, the seed layer having an exposed surface; (b) immersing the substrate in a plating solution; (c) electrodepositing a copper-containing film on the exposed surface of the seed layer, the copper-containing film having a first surface; (d) maintaining the substrate in an immersed state within the plating solution; (e) electrodepositing a further copper-containing film from the plating solution onto the first surface; (f) removing the substrate from the plating solution; and (g) drying the substrate.

摘要翻译： 一种抗电镀铜膜结构和形成该结构的方法。 膜结构含有高杂质含量，耐晶粒生长，具有优良的冶金，热机械和电学性能。 该方法包括以下步骤：（a）至少间接地在基底上提供种子层，籽晶层具有暴露表面; （b）将基板浸入电镀液中; （c）在种子层的暴露表面上电沉积含铜膜，所述含铜膜具有第一表面; （d）将所述基板保持在所述电镀液中的浸渍状态; （e）将另外的含铜膜从所述电镀溶液电沉积到所述第一表面上; （f）从电镀液中除去基板; 和（g）干燥基材。

公开(公告)号：US07560692B2

公开(公告)日：2009-07-14

申请号：US11617386

申请日：2006-12-28

申请人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

发明人： Keith E. Barton ,  Steven H. Boettcher ,  John G. Gaudiello ,  Leon J. Kimball ,  Yun-Yu Wang

IPC分类号： G01N1/32 ,  G01N23/04

CPC分类号： G01N1/2806

摘要： A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

摘要翻译： 适用于电子全息术的高品质电子显微镜样品通过形成填充有TEOS氧化物的标记物，并通过反复施加多层粘合剂，然后在每次涂布之后进行相对低温固化来制备。 TEOS氧化物标记在抛光期间容易看到，具有与半导体材料相似的抛光速率，并减少样品制备过程中的污染。 通过相对低温固化分离的粘合剂的重复施加增加了粘合剂材料对半导体材料的粘合强度，而不会使其变得太脆。 这导致样品制备过程的改进的控制和产率。

公开(公告)号：US07214935B2

公开(公告)日：2007-05-08

申请号：US10711690

申请日：2004-09-30

申请人： Thomas A. Bauer ,  Steven H. Boettcher ,  Anthony G. Domenicucci ,  John G. Gaudiello ,  Leon J. Kimball ,  Jeffrey S. McMurray ,  Yun-Yu Wang

发明人： Thomas A. Bauer ,  Steven H. Boettcher ,  Anthony G. Domenicucci ,  John G. Gaudiello ,  Leon J. Kimball ,  Jeffrey S. McMurray ,  Yun-Yu Wang

IPC分类号： G01N1/32 ,  G01N23/04

CPC分类号： G01N1/32 ,  G01N23/04 ,  H01J2237/2614

摘要： A method for preparing a transmission electron microscopy (TEM) sample for electron holography includes forming a sacrificial material over an area of interest on the sample, and polishing the sample to a desired thickness, wherein the area of interest is protected from rounding during the polishing. The sacrificial material is removed from the sample following the polishing.

摘要翻译： 制备用于电子全息术的透射电子显微镜（TEM）样品的方法包括在样品上的感兴趣区域上形成牺牲材料，并将样品抛光至所需厚度，其中在抛光过程中保护感兴趣区域免于四舍五入 。 抛光后，从样品中除去牺牲材料。