公开(公告)号：US20070273394A1

公开(公告)日：2007-11-29

申请号：US10558695

申请日：2004-06-07

申请人： Philip Tanner ,  Peter Johnson ,  David Thiel ,  Takeharu Suzuki ,  Richard Adamec ,  Peter Beadle

发明人： Philip Tanner ,  Peter Johnson ,  David Thiel ,  Takeharu Suzuki ,  Richard Adamec ,  Peter Beadle

IPC分类号： G01R27/26

CPC分类号： A01G25/167 ,  G01D21/02 ,  G01F1/6845 ,  G01F1/692 ,  G01N27/223 ,  G01N33/246 ,  G01P5/12 ,  G01P13/02

摘要： Multi functional sensors are described. A silicon based sensor utilizes metal layers arranged as resistors around a central pair if resistors separated by a humidity sensitive polymer with one of the central resistors being a heater. This enables temperature humidity wind speed and direction to be measured. In another embodiment an array of resistors is printed onto a flexible substrate to form the basis of an array of sensors. A soil moisture sensor, which is also useful as a leaf wetness sensor, incorporates a novel self calibrating capacitive sensor structure. The flexible substrate is rolled into a stake that can be inserted in the soil so that below ground sensors measure soil moisture and above ground sensors measure temperature, light, humidity, wind speed and direction.

摘要翻译： 描述了多功能传感器。 硅基传感器利用金属层作为中心对周围的电阻器布置，如果电阻器被湿度敏感的聚合物隔开，其中一个中央电阻器是加热器。 这样可以测量温度湿度风速和方向。 在另一个实施例中，将电阻器阵列印刷到柔性基板上以形成传感器阵列的基础。 土壤湿度传感器也可用作叶湿度传感器，结合了一种新型的自校准电容传感器结构。 将柔性基材卷成可插入土壤的桩，以便地下传感器测量土壤湿度，地上传感器测量温度，光照，湿度，风速和方向。

公开(公告)号：US20160251318A1

公开(公告)日：2016-09-01

申请号：US14241374

申请日：2012-08-28

申请人： Stephen Martin Courtney ,  Michael Prime ,  William Mitchell ,  Christopher John Brown ,  Paula C. De Aguiar Pena ,  Peter Johnson ,  Celia Dominguez ,  Leticia M. Toledo-Sherman ,  Ignacio Munoz

发明人： Stephen Martin Courtney ,  Michael Prime ,  William Mitchell ,  Christopher John Brown ,  Paula C. De Aguiar Pena ,  Peter Johnson ,  Celia Dominguez ,  Leticia M. Toledo-Sherman ,  Ignacio Munoz

IPC分类号： C07D239/28 ,  C07D403/12 ,  C07D405/12 ,  C07D405/14 ,  C07D401/12 ,  C07D405/04 ,  C07D491/048 ,  C07D491/052 ,  C07H13/10 ,  C07D413/04 ,  C07D471/04 ,  C07D409/04 ,  C07D417/04 ,  C07D403/10 ,  C07D405/10 ,  C07D401/04

CPC分类号： C07D239/28 ,  C07D239/42 ,  C07D401/04 ,  C07D401/12 ,  C07D403/04 ,  C07D403/10 ,  C07D403/12 ,  C07D405/04 ,  C07D405/10 ,  C07D405/12 ,  C07D405/14 ,  C07D409/04 ,  C07D413/04 ,  C07D417/04 ,  C07D471/04 ,  C07D491/048 ,  C07D491/052 ,  C07H13/10

摘要： Certain chemical entities are provided herein. Also provided are pharmaceutical compositions comprising at least one chemical entity and one or more pharmaceutically acceptable vehicle. Methods of treating patients suffering from certain diseases and disorders responsive to the inhibition of KMO activity are described, which comprise administering to such patients an amount of at least one chemical entity effective to reduce signs or symptoms of the disease or disorder are disclosed. These diseases include neurodegenerative disorders such as Huntington's disease. Also described are methods of treatment include administering at least one chemical entity as a single active agent or administering at least one chemical entity in combination with one or more other therapeutic agents. Also provided are methods for screening compounds capable of inhibiting KMO activity.

摘要翻译： 本文提供了某些化学实体。 还提供了包含至少一种化学物质和一种或多种药学上可接受的载体的药物组合物。 描述了治疗患有对KMO活性的抑制作用的某些疾病和病症的患者的方法，其包括给予这些患者一定量的至少一种有效减少疾病或病症的体征或症状的化学实​​体。 这些疾病包括神经变性疾病如亨廷顿氏病。 还描述了治疗方法，包括给予至少一种作为单一活性剂的化学实体或与一种或多种其它治疗剂组合施用至少一种化学实体。 还提供了用于筛选能够抑制KMO活性的化合物的方法。

公开(公告)号：US08674418B2

公开(公告)日：2014-03-18

申请号：US13214069

申请日：2011-08-19

申请人： Anindya Poddar ,  Vijaylaxmi Khanolkar ,  Ashok S. Prabhu ,  Peter Johnson

发明人： Anindya Poddar ,  Vijaylaxmi Khanolkar ,  Ashok S. Prabhu ,  Peter Johnson

IPC分类号： H01L31/062 ,  H01L21/70 ,  H01L23/552

CPC分类号： H01F17/0013 ,  H01F27/32 ,  H01F27/36 ,  H01F2017/008

摘要： An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.

摘要翻译： 描述了一种具有布置在一对线圈之间的改进的电隔离层和其构造方法的电感器件。

公开(公告)号：US08314676B1

公开(公告)日：2012-11-20

申请号：US13098656

申请日：2011-05-02

申请人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

发明人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

IPC分类号： H01F5/00 ,  H01F7/06 ,  H01L27/08

CPC分类号： H01F17/0033 ,  H01F41/046 ,  Y10T29/4902 ,  Y10T29/49075 ,  Y10T29/49078

摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.

摘要翻译： 可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。 受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层层叠件具有水平底座以及从底座基本垂直向上延伸的第一和第二间隔开的侧壁，以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

公开(公告)号：US20120280781A1

公开(公告)日：2012-11-08

申请号：US13098656

申请日：2011-05-02

申请人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

发明人： Peter Smeys ,  Andrei Papou ,  Peter Johnson ,  Anuraag Mohan

IPC分类号： H01F27/24 ,  H01F41/02

CPC分类号： H01F17/0033 ,  H01F41/046 ,  Y10T29/4902 ,  Y10T29/49075 ,  Y10T29/49078

摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.

摘要翻译： 可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。 受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层片具有水平底座和第一和第二间隔开的侧壁，从侧面基本垂直向上延伸以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

公开(公告)号：US08222065B1

公开(公告)日：2012-07-17

申请号：US12587139

申请日：2009-10-02

申请人： Peter Smeys ,  Peter Johnson ,  Gokhan Percin

发明人： Peter Smeys ,  Peter Johnson ,  Gokhan Percin

IPC分类号： H01L29/72

CPC分类号： B06B1/0292 ,  H01L27/0688

摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide features. For a particular embodiment, the SOI wafer comprises a single crystal epitaxial layer, a buried oxide layer and a silicon layer, and the single crystal epitaxial layer is bonded to the planarized oxide features, after which the silicon layer and the buried oxide layer of the SOI wafer are removed, leaving the single crystal epitaxial layer bonded to the oxide layer.

摘要翻译： 提供一种用于形成电容微加工超声换能器（CMUT）的方法，其包括在硅晶片中的CMUT控制芯片外部形成氧化物特征。 氧化物的特征被平坦化。 绝缘体上硅（SOI）晶片与平坦化的氧化物特征结合。 对于特定实施例，SOI晶片包括单晶外延层，掩埋氧化物层和硅层，并且单晶外延层结合到平坦化的氧化物特征，之后硅层和掩埋氧化物层 去除SOI晶片，留下单晶外延层与氧化物层结合。

公开(公告)号：US20120161294A1

公开(公告)日：2012-06-28

申请号：US12978492

申请日：2010-12-24

申请人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

发明人： Peter J. Hopper ,  Peter Johnson ,  Peter Smeys ,  William French

IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/66

CPC分类号： H01L22/20 ,  H01L22/14 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/0802 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.

摘要翻译： 在每个晶片被形成为包括暴露高精度电路的电路内部的可调节电路元件的开口的过程中，每个具有多个高精度电路和相应的微调控制电路的多个晶片被批量修整。 高精度电路和微调控制电路在修整阶段通过沿着锯木街道行进的金属轨迹进行电激活。 该方法将晶片接触结构连接到每个晶片以电激活金属迹线。 该方法将具有晶片接触结构的晶片放置在当高精度电路的实际输出电压与高精度电路的预测输出电压不匹配时，暴露的可调节电路元件被电镀或阳极化的解决方案中。

公开(公告)号：US20110260248A1

公开(公告)日：2011-10-27

申请号：US12768295

申请日：2010-04-27

申请人： Peter Smeys ,  Peter Johnson ,  Peter J. Hopper ,  William French

发明人： Peter Smeys ,  Peter Johnson ,  Peter J. Hopper ,  William French

IPC分类号： H01L29/786 ,  H01L21/768

CPC分类号： H01L27/1203 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/522 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： A silicon-on-insulator (SOI) wafer is formed to have through-the-wafer contacts, and trench based interconnect structures on the back side of the SOI wafer that electrically connect the through-the-wafer contacts. In addition, selected ones of the through-the-wafer contacts bias the bodies of the MOS transistors.

摘要翻译： 形成绝缘体上硅（SOI）晶片以具有贯穿晶片的触点，以及SOI晶片的背侧上的沟槽基互连结构，其电连接晶片间的触点。 此外，通过晶片间接触的选定的一个偏压MOS晶体管的主体。

公开(公告)号：US08044755B2

公开(公告)日：2011-10-25

申请号：US12082209

申请日：2008-04-09

申请人： Peter Smeys ,  Peter Johnson

发明人： Peter Smeys ,  Peter Johnson

IPC分类号： H01F5/00

CPC分类号： H01F17/0006 ,  H01F41/046 ,  H01F2017/0066 ,  H01F2017/0086 ,  H01L28/10 ,  Y10T29/4902 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913

摘要： A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.

摘要翻译： 在半导体管芯的顶表面上形成可伸缩的MEMS电感器。 MEMS电感器包括多个磁性下层叠体，位于磁性下部叠片之上并与之隔开的圆形迹线以及位于圆形迹线之上并与圆形迹线隔开的多个上层叠体。

公开(公告)号：US07902661B2

公开(公告)日：2011-03-08

申请号：US12643924

申请日：2009-12-21

申请人： Peter Smeys ,  Peter Johnson ,  Peter Deane ,  Reda R. Razouk

发明人： Peter Smeys ,  Peter Johnson ,  Peter Deane ,  Reda R. Razouk

IPC分类号： H01L23/04 ,  H01L23/12 ,  H01L23/053 ,  H01L23/23

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00

摘要： Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit.

摘要翻译： 描述了用于形成集成电路封装的各种装置和方法。 本发明的一个方面涉及一种集成电路封装，其中一个或多个集成电路嵌入在基片中并被一层可光成像的环氧树脂覆盖。 基板可以由各种材料制成，包括硅，石英和玻璃。 集成电路位于衬底的顶表面中的空腔内。 环氧树脂层形成在衬底的顶表面和集成电路的有源面上。 在环氧树脂层上形成互连层并与集成电路电耦合。