公开(公告)号：US20090045513A1

公开(公告)日：2009-02-19

申请号：US12193561

申请日：2008-08-18

申请人： Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

发明人： Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

摘要翻译： 一种包括半导体芯片的半导体芯片封装，所述半导体芯片包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US20090039491A1

公开(公告)日：2009-02-12

申请号：US12104333

申请日：2008-04-16

申请人： Pyoung-Wan KIM ,  Teak-Hoon LEE ,  Chul-Yong JANG

发明人： Pyoung-Wan KIM ,  Teak-Hoon LEE ,  Chul-Yong JANG

IPC分类号： H01L23/00 ,  H01L21/50

CPC分类号： H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599

摘要： In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

摘要翻译： 在一个实施例中，半导体封装包括第一绝缘体和具有第一有源表面和与第一有源表面相对的第一后表面的第一半导体芯片。 第一半导体芯片设置在第一绝缘体内。 第一活性表面被第一绝缘体暴露。 第一后表面基本上被第一绝缘体包围。 半导体封装包括在第一绝缘体内并邻近第一半导体芯片的一侧的柱。

公开(公告)号：US20090134528A1

公开(公告)日：2009-05-28

申请号：US12253734

申请日：2008-10-17

申请人： Teak-Hoon LEE ,  Nam-Seog KIM ,  Pyoung-Wan KIM ,  Chul-Yong JANG

发明人： Teak-Hoon LEE ,  Nam-Seog KIM ,  Pyoung-Wan KIM ,  Chul-Yong JANG

IPC分类号： H01L23/52

CPC分类号： H01L23/5389 ,  H01L21/486 ,  H01L23/49816 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2225/06524 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Provided are a semiconductor package, an electronic device including the semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes semiconductor chips mounted on a carrier, a first insulating layer sealing the semiconductor chips, first via-holes which are formed in the first insulating layer and expose a portion of each of the semiconductor chips, a first conductive pattern which is filled in the first via-holes and electrically connected to each of the semiconductor chips, and an external terminal which is electrically connected to the first conductive pattern. The semiconductor package is manufactured by performing an encapsulating process and a via-hole process.

摘要翻译： 提供半导体封装，包括半导体封装的电子器件和制造半导体封装的方法。 半导体封装包括安装在载体上的半导体芯片，密封半导体芯片的第一绝缘层，形成在第一绝缘层中并暴露每个半导体芯片的一部分的第一通孔，填充了第一导电图案 在第一通孔中并且电连接到每个半导体芯片，以及电连接到第一导电图案的外部端子。 通过执行封装处理和通孔处理来制造半导体封装。

公开(公告)号：US20090096071A1

公开(公告)日：2009-04-16

申请号：US12240036

申请日：2008-09-29

申请人： Pyoung-Wan KIM ,  Eun-Chul AHN ,  Teak-Hoon LEE ,  Chul-Yong JANG

发明人： Pyoung-Wan KIM ,  Eun-Chul AHN ,  Teak-Hoon LEE ,  Chul-Yong JANG

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/3114 ,  H01L2224/04105 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

摘要翻译： 半导体封装可以包括半导体芯片，模制半导体芯片的模制层和跨越半导体芯片和模制层之间的界面延伸并将半导体芯片连接到外部的互连，其中互连的形状是 沿其长度改变。 根据本发明，即使对互连件施加机械应力或热应力，在互连中也不会发生裂纹，也不会断开互连。 因此，提高了半导体封装的可靠性。

公开(公告)号：US20080265432A1

公开(公告)日：2008-10-30

申请号：US12113009

申请日：2008-04-30

申请人： Min-Ho O ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Pyoung-Wan KIM ,  Hyeon HWANG ,  Teak-Hoon LEE

发明人： Min-Ho O ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Pyoung-Wan KIM ,  Hyeon HWANG ,  Teak-Hoon LEE

IPC分类号： H01L23/49

CPC分类号： H01L24/85 ,  H01L23/3121 ,  H01L23/562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/27013 ,  H01L2224/29007 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83194 ,  H01L2224/83801 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： A multi-chip package includes a mounting substrate, a first semiconductor chip, a second semiconductor chip, a reinforcing member, conductive wires and an encapsulant. The first semiconductor chip is disposed on the mounting substrate. The second semiconductor chip is disposed on the first semiconductor chip. An end portion of the second semiconductor chip protrudes from a side portion of the first semiconductor chip. A reinforcing member is disposed on an overlapping region of the second semiconductor chip where the second semiconductor chip overlaps with the side portion of the first semiconductor chip such that the reinforcing member decreases downward bending of the second semiconductor chip from the side portion of the first semiconductor chip. The conductive wires electrically connect the first and second semiconductor chips to the mounting substrate. The encapsulant is disposed on the mounting substrate to cover the first and second semiconductor chips and the conductive wires.

摘要翻译： 多芯片封装包括安装基板，第一半导体芯片，第二半导体芯片，加强构件，导线和密封剂。 第一半导体芯片设置在安装基板上。 第二半导体芯片设置在第一半导体芯片上。 第二半导体芯片的端部从第一半导体芯片的侧部突出。 加强构件设置在第二半导体芯片的重叠区域上，其中第二半导体芯片与第一半导体芯片的侧部重叠，使得加强构件从第一半导体的侧部减小第二半导体芯片的向下弯曲 芯片。 导线将第一和第二半导体芯片电连接到安装基板。 密封剂设置在安装基板上以覆盖第一和第二半导体芯片和导线。

公开(公告)号：US20080283996A1

公开(公告)日：2008-11-20

申请号：US12121490

申请日：2008-05-15

申请人： Min-Ho O ,  Jong-Ho LEE ,  Eun-Chul AHN ,  Pyoung-Wan KIM

发明人： Min-Ho O ,  Jong-Ho LEE ,  Eun-Chul AHN ,  Pyoung-Wan KIM

IPC分类号： H01L23/49 ,  H01L23/538

CPC分类号： H01L24/85 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.

摘要翻译： 提供了使用芯片嵌入式插入器基板的半导体封装。 芯片嵌入式插入器基板包括：包括多个芯片焊盘的芯片; 具有安装在其上的芯片并且包括用于重新分配芯片焊盘的多个再分配焊盘的衬底; 用于将芯片焊盘连接到再分配焊盘的接合线; 保护层，其具有用于在掩埋所述芯片和所述基板的同时露出所述再分布焊盘的通孔; 以及通过通孔连接到再分配焊盘的通孔。 包括各种尺寸的芯片的半导体封装使用芯片嵌入式插入器基板来制造。