公开(公告)号：US4782381A

公开(公告)日：1988-11-01

申请号：US062005

申请日：1987-06-12

Applicant: Richard C. Ruby ,  Clinton Chao

Inventor： Richard C. Ruby ,  Clinton Chao

IPC: H01L27/01 ,  H01L23/538 ,  H01L23/64 ,  H01L23/48 ,  H01C1/012 ,  H01L29/90 ,  H01L39/02

CPC classification number: H01L23/538 ,  H01L23/647 ,  H01L2224/16225 ,  H01L2924/1305 ,  H01L2924/3011

Abstract: A chip carrier for carrying integrated circuit chips is provided. Instead of placing individual circuit components either in the chips or next to them, the components are placed in or near the substrate of the chip carrier. This frees up expensive real-estate for logic chips at the chip level presently occupied by the components. The substrate of the carrier acts as a large heat sink to dissipate power generated by the components.

Abstract translation: 提供了用于承载集成电路芯片的芯片载体。 代替将单独的电路组件放置在芯片中或其旁边，将组件放置在芯片载体的衬底中或附近。 这可以在目前由组件占用的芯片级别上释放昂贵的逻辑芯片。 载体的基板用作大的散热器，以消散由部件产生的电力。

公开(公告)号：US08426256B2

公开(公告)日：2013-04-23

申请号：US12700929

申请日：2010-02-05

Applicant: C. W. Hsiao ,  Bo-I Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

Inventor： C. W. Hsiao ,  Bo-I Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

IPC: H01L21/00

CPC classification number: H01L23/3114 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/00

Abstract: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

Abstract translation: 公开了一种形成堆叠的模具结构的方法。 多个管芯分别与晶片的第一表面上的多个半导体芯片接合。 在多个管芯和晶片的第一表面上形成封装结构。 封装结构覆盖晶片的第一表面的中心部分并且使晶片的边缘部分露出。 在晶片的边缘部分的第一表面上形成保护材料。

公开(公告)号：US08174129B2

公开(公告)日：2012-05-08

申请号：US12853711

申请日：2010-08-10

Applicant: Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

Inventor： Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/147 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Abstract translation: 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装基板优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个迹线，连接BGA球和焊料凸块。 半导体芯片可以安装在焊料凸块上。 硅基薄封装衬底可以用作半导体芯片的载体。

公开(公告)号：US07977155B2

公开(公告)日：2011-07-12

申请号：US11800386

申请日：2007-05-04

Applicant: Chien-Hsiun Lee ,  Clinton Chao ,  Ming-Chung Sung ,  Tjandra Winata Karta

Inventor： Chien-Hsiun Lee ,  Clinton Chao ,  Ming-Chung Sung ,  Tjandra Winata Karta

IPC: H01L21/00 ,  H01L21/66

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.

Abstract translation: 提供一种封装集成电路结构的方法。 该方法包括在晶片的表面上提供具有接合导体的晶片，并将化合物底部填充物施加到晶片的表面上。 复合底层填充物包括底部填充材料和助焊剂材料。 然后，在施加化合物底部填充物的步骤之后，将晶片接合在晶片上，其中在该芯片上的焊料凸块与接合导体接合。

公开(公告)号：US07804177B2

公开(公告)日：2010-09-28

申请号：US11493375

申请日：2006-07-26

Applicant: Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

Inventor： Szu Wei Lu ,  Clinton Chao ,  Ann Luh ,  Tjandra Winata Karta ,  Jerry Tzou ,  Kuo-Chin Chang

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/147 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of through-hole vias are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips.

Abstract translation: 硅基薄封装衬底用于封装半导体芯片。 硅基薄封装基板优选具有小于约200μm的厚度。 在硅基薄封装衬底中形成多个通孔，连接BGA球和焊料凸块。 硅基薄封装衬底可以用作半导体芯片的载体。

公开(公告)号：US20080296697A1

公开(公告)日：2008-12-04

申请号：US11807505

申请日：2007-05-29

Applicant: Chao-Shun Hsu ,  Clinton Chao ,  Mark Shane Peng

Inventor： Chao-Shun Hsu ,  Clinton Chao ,  Mark Shane Peng

IPC: H01L23/525

CPC classification number: H01L21/76886 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/5382 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/19011 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Various structures of a programmable semiconductor interposer for electronic packaging are described. An array of semiconductor devices having various values is formed in said interposer. A user can program said interposer and form a “virtual” device having a desired value by selectively connecting various one of the array of devices to contact pads formed on the surface of said interposer. An inventive electronic package structure includes a standard interposer having an array of unconnected devices of various values and a device selection unit, which selectively connects various one of the array of devices in said standard interposer to an integrated circuit die encapsulated in said electronic package. Methods of forming said programmable semiconductor interposer and said electronic package are also illustrated.

Abstract translation: 描述了用于电子封装的可编程半导体插入器的各种结构。 在所述插入器中形成具有各种值的半导体器件阵列。 用户可以对所述插入器进行编程，并通过选择性地将所述器件阵列中的一个连接到形成在所述插入器的表面上的接触焊盘来形成具有期望值的“虚拟”器件。 本发明的电子封装结构包括具有各种值的未连接器件阵列的标准插入器和器件选择单元，该器件选择单元选择性地将所述标准插入器中的各种器件阵列连接到封装在所述电子封装中的集成电路管芯。 还示出了形成所述可编程半导体插入器和所述电子封装的方法。

公开(公告)号：US20080073747A1

公开(公告)日：2008-03-27

申请号：US11525603

申请日：2006-09-22

Applicant: Clinton Chao ,  C.S. Hsu ,  Mark Shane Peng ,  Szu Wei Lu ,  Tjandra Winata Karta

Inventor： Clinton Chao ,  C.S. Hsu ,  Mark Shane Peng ,  Szu Wei Lu ,  Tjandra Winata Karta

IPC: H01L29/00 ,  H01L21/331

CPC classification number: H01L25/0657 ,  H01L21/76 ,  H01L21/823481 ,  H01L23/481 ,  H01L23/585 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/014 ,  H01L2924/013 ,  H01L2924/00014

Abstract: An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.

公开(公告)号：US08247267B2

公开(公告)日：2012-08-21

申请号：US12045858

申请日：2008-03-11

Applicant: Chien Hsiun Lee ,  Clinton Chao ,  Mirng Ji Lii ,  Tjandra Winata Karta

Inventor： Chien Hsiun Lee ,  Clinton Chao ,  Mirng Ji Lii ,  Tjandra Winata Karta

IPC: H01L21/00

CPC classification number: H01L24/97 ,  H01L21/563 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73203 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A wafer level integrated circuit assembly method is conducted as follows. First, a mother device wafer with plural first posts is provided. The first posts are used for electrical connection and are made of copper according to an embodiment. Solder is sequentially formed on the first posts. The solder is preferably pre-formed on a wafer, and the locations of the solder correspond to the first posts of the mother device wafer. Consequently, the solder can be formed on or adhered to the first posts by placing the wafer having pre-formed solder onto the first posts. Plural dies having plural second posts corresponding to the first posts are placed onto the mother device wafer. Then, the solder is reflowed to bond the first and second posts, and the mother device wafer is diced.

Abstract translation: 晶圆级集成电路组装方法如下进行。 首先，提供具有多个第一柱的母装置晶片。 根据实施例，第一柱用于电连接并且由铜制成。 在第一柱上依次形成焊料。 焊料优选在晶片上预先形成，并且焊料的位置对应于母体器件晶片的第一柱。 因此，通过将具有预成形焊料的晶片放置在第一柱上，可以在第一柱上形成或粘附焊料。 具有与第一柱对应的多个第二柱的多个模具被放置在母体装置晶片上。 然后，回流焊接以粘接第一和第二柱，并且母体装置晶片被切割。

公开(公告)号：US07795735B2

公开(公告)日：2010-09-14

申请号：US11689264

申请日：2007-03-21

Applicant: Chao-Shun Hsu ,  Chen-Yao Tang ,  Clinton Chao ,  Mark Shane Peng

Inventor： Chao-Shun Hsu ,  Chen-Yao Tang ,  Clinton Chao ,  Mark Shane Peng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/46 ,  H01L21/4763

CPC classification number: H01L25/0655 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/522 ,  H01L2924/0002 ,  Y10T428/12229 ,  H01L2924/00

Abstract: A method for forming a single die includes forming at least one first active device over a first substrate and at least one first metallic layer coupled to the first active device. At least one second metallic layer is formed over a second substrate, wherein the second substrate does not include any active device. The at least one first metallic layer is bonded with the at least one second metallic layer such that the first substrate and the second substrate constitute a single die.

Abstract translation: 用于形成单个管芯的方法包括在第一衬底上形成至少一个第一有源器件以及耦合到第一有源器件的至少一个第一金属层。 在第二衬底上形成至少一个第二金属层，其中第二衬底不包括任何有源器件。 所述至少一个第一金属层与所述至少一个第二金属层接合，使得所述第一基板和所述第二基板构成单个管芯。

公开(公告)号：US07494846B2

公开(公告)日：2009-02-24

申请号：US11716104

申请日：2007-03-09

Applicant: Chao-Shun Hsu ,  Louis Liu ,  Clinton Chao ,  Mark Shane Peng

Inventor： Chao-Shun Hsu ,  Louis Liu ,  Clinton Chao ,  Mark Shane Peng

IPC: H01L21/8242

CPC classification number: G11C5/02 ,  G11C5/04 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A semiconductor structure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit; and a first plurality of input/output (I/O) pads on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the first and the second identification circuits are programmed differently from each other; and a second plurality of I/O pads on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned to and connected to one of the respective second plurality of I/O pads. The second semiconductor die is vertically aligned to and bonded on the first semiconductor die.

Abstract translation: 半导体结构包括与第一半导体管芯相同的第一半导体管芯和第二半导体管芯。 第一半导体管芯包括第一识别电路; 以及在第一半导体管芯的表面上的第一多个输入/输出（I / O）焊盘。 第二半导体管芯包括第二识别电路，其中第一和第二识别电路被编程为彼此不同; 以及在第二半导体管芯的表面上的第二多个I / O焊盘。 第一组多个I / O焊盘中的每一个垂直对准并连接到相应的第二多个I / O焊盘之一。 第二半导体管芯垂直对齐并接合在第一半导体管芯上。