公开(公告)号：US20140017397A1

公开(公告)日：2014-01-16

申请号：US14030579

申请日：2013-09-18

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Mi Sun HWANG ,  Jae Joon Lee ,  Myung Sam Kang

IPC: H05K3/10

CPC classification number: H05K3/10 ,  H05K1/0271 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/09136

Abstract: A method of manufacturing a printed circuit board includes arranging a core layer in which a bending prevention portion of at least two layers that are metal layers having different thermal expansion coefficients is disposed between a plurality of insulating members; forming a circuit pattern so as to have a desired pattern on at least one of the inside of the core layer and an outer face of the core layer; and forming an insulating layer including an opening portion that exposes the circuit pattern on the core layer.

Abstract translation: 制造印刷电路板的方法包括：布置芯层，其中在多个绝缘构件之间布置有具有不同热膨胀系数的金属层的至少两层的至少两层的弯曲防止部分; 形成电路图案，以便在芯层的内部和芯层的外表面中的至少一个上具有期望的图案; 以及形成包括露出所述芯层上的电路图案的开口部分的绝缘层。

公开(公告)号：US10395814B2

公开(公告)日：2019-08-27

申请号：US15660640

申请日：2017-07-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ki Seok Kim ,  Ye Jeong Kim ,  Myung Sam Kang ,  Kwang Hee Kwon

IPC: H01F5/00 ,  H01F27/28 ,  H01F27/29 ,  H01F41/04 ,  H01F27/32 ,  H01F41/12 ,  H01F17/00

Abstract: A coil electronic component includes: a plurality of stacked coil layers each including coil patterns including anisotropic plating layers; conductive vias connecting the coil patterns formed on different coil layers to each other; and external electrodes electrically connected to the plurality of coil layers.

公开(公告)号：US20150364407A1

公开(公告)日：2015-12-17

申请号：US14607074

申请日：2015-01-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Se Rang IM ,  Seung Eun Lee ,  Seung Yeop Kook ,  Myung Sam Kang

IPC: H01L23/498 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: There are provided a package board and a package using the same. The package board according to an exemplary embodiment of the present disclosure includes: an insulating layer; a circuit pattern formed in the insulating layer; a capacitor formed on a whole surface of a horizontal plane in the insulating layer; and a first via penetrating through the capacitor and electrically connecting the circuit patterns each formed on upper and lower portions of the capacitor to each other.

Abstract translation: 提供了一个包装板和一个使用它的包装。 根据本公开的示例性实施例的封装板包括：绝缘层; 形成在绝缘层中的电路图案; 形成在绝缘层的水平面的整个表面上的电容器; 以及穿过电容器并且将形成在电容器的上部和下部上的电路图案彼此电连接的第一通孔。

公开(公告)号：US20150351228A1

公开(公告)日：2015-12-03

申请号：US14463468

申请日：2014-08-19

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jin Seon PARK ,  Myung Sam Kang ,  Seung Eun Lee ,  Seung Yeop Kook ,  Ki Jung Sung ,  Ju Hee Park ,  Je Gwang Yoo

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/40 ,  H05K1/11 ,  H01L23/522 ,  H05K3/30

CPC classification number: H01L21/6835 ,  H01L21/486 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/18 ,  Y10T29/49131

Abstract: There are provided a package board and a method for manufacturing the same. According to an exemplary embodiment of the present disclosure, a package board includes: a first insulating layer; a second insulating layer formed beneath the first insulating layer; a capacitor embedded in the first insulating layer and including a first electrode, a second electrode, and a dielectric layer formed between the first electrode and the second electrode; circuit layers formed on the first insulating layer and the second insulating layer; and a via formed between the capacitor and the circuit layers or between the circuit layers formed on the first insulating layer and the second insulating layer to electrically connect thererbetween, wherein an upper surface of the first electrode is formed to be exposed from the first insulating layer.

Abstract translation: 提供了一种封装板及其制造方法。 根据本公开的示例性实施例，封装板包括：第一绝缘层; 形成在第一绝缘层下面的第二绝缘层; 嵌入在所述第一绝缘层中并且包括形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质层的电容器; 形成在第一绝缘层和第二绝缘层上的电路层; 以及形成在电容器和电路层之间或形成在第一绝缘层和第二绝缘层之间的电路层之间的通孔，以在其间电连接，其中形成第一电极的上表面以从第一绝缘层 。

公开(公告)号：US08945993B2

公开(公告)日：2015-02-03

申请号：US14028837

申请日：2013-09-17

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC: H01L21/332 ,  H01L21/768 ,  H01L23/13 ,  H01L23/00 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method of manufacturing a ball grid array substrate includes: forming a first circuit pattern and a second circuit pattern on a first metal carrier and a second metal carrier, respectively; stacking a first insulating layer and a second insulating layer with a separable material interposed therebetween, wherein each of the first and second insulating layers has first and second surfaces opposing each other, and the first surface contacts the separable material; burying the first and second circuit patterns in the second surfaces of the first and second insulating layers, respectively; removing the first and second metal carriers; removing the separable material to separate the first and second insulating layers from each other; and forming an opening in each of the first and second insulating layers to connect the first and second surfaces with each other. The method may also be part of a process for manufacturing a semiconductor package.

Abstract translation: 制造球栅阵列基板的方法包括：分别在第一金属载体和第二金属载体上形成第一电路图案和第二电路图案; 堆叠具有插入其间的可分离材料的第一绝缘层和第二绝缘层，其中第一和第二绝缘层中的每一个具有彼此相对的第一和第二表面，并且第一表面接触可分离材料; 将第一和第二电路图案分别埋在第一和第二绝缘层的第二表面中; 去除所述第一和第二金属载体; 去除可分离材料以将第一和第二绝缘层彼此分离; 以及在所述第一绝缘层和所述第二绝缘层的每一个中形成开口以将所述第一表面和所述第二表面彼此连接。 该方法也可以是用于制造半导体封装的工艺的一部分。

公开(公告)号：US08720048B2

公开(公告)日：2014-05-13

申请号：US14030579

申请日：2013-09-18

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Mi Sun Hwang ,  Jae Joon Lee ,  Myung Sam Kang

IPC: H05K3/36 ,  H01K3/10

CPC classification number: H05K3/10 ,  H05K1/0271 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/09136

Abstract: A method of manufacturing a printed circuit board includes arranging a core layer in which a bending prevention portion of at least two layers that are metal layers having different thermal expansion coefficients is disposed between a plurality of insulating members; forming a circuit pattern so as to have a desired pattern on at least one of the inside of the core layer and an outer face of the core layer; and forming an insulating layer including an opening portion that exposes the circuit pattern on the core layer.

Abstract translation: 制造印刷电路板的方法包括：布置芯层，其中在多个绝缘构件之间布置有具有不同热膨胀系数的金属层的至少两层的至少两层的弯曲防止部分; 形成电路图案，以便在芯层的内部和芯层的外表面中的至少一个上具有期望的图案; 以及形成包括露出所述芯层上的电路图案的开口部分的绝缘层。

公开(公告)号：US20140102766A1

公开(公告)日：2014-04-17

申请号：US13831534

申请日：2013-03-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Da Hee Kim ,  Yoong Oh ,  Ki Young Yoo ,  Han Ul Lee ,  Myung Sam Kang ,  Ki Hwan Kim

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/46 ,  H05K1/0298 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2203/025 ,  H05K2203/0733 ,  Y10T29/49155

Abstract: Disclosed herein is a multi-layer type coreless substrate, including: a first insulating layer including at least one first pillar; a plurality of insulating layers laminated on one surface or both surfaces of the first insulating layer, each including at least one circuit layer and at least another pillar connected to the circuit layer; and a plurality of outermost circuit layers contacting a pillar disposed on an outermost insulating layer of the plurality of insulating layers.

Abstract translation: 本文公开了一种多层型无芯基板，包括：第一绝缘层，其包括至少一个第一柱; 层叠在第一绝缘层的一个表面或两个表面上的多个绝缘层，每个绝缘层包括至少一个电路层和至少另一个连接到电路层的柱; 以及与设置在所述多个绝缘层的最外绝缘层上的柱接触的多个最外层电路层。

公开(公告)号：US11605484B2

公开(公告)日：2023-03-14

申请号：US16803315

申请日：2020-02-27

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Woon Chul Choi ,  Myung Jun Park ,  Hye Min Bang ,  Jun Ah ,  Myung Sam Kang ,  Jung Hyuk Jung

IPC: H01F17/00 ,  H01F27/255 ,  H01F41/04

Abstract: A multilayer seed pattern inductor includes a magnetic body and an internal coil part. The magnetic body contains a magnetic material. The internal coil part is embedded in the magnetic body and includes connected coil conductors disposed on two opposing surfaces of an insulating substrate. Each of the coil conductors includes a seed pattern formed of at least two layers, a surface coating layer covering the seed pattern, and an upper plating layer formed on an upper surface of the surface coating layer.

公开(公告)号：US11488768B2

公开(公告)日：2022-11-01

申请号：US16408746

申请日：2019-05-10

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Sa Yong Lee ,  Myung Sam Kang

IPC: H01F27/32 ,  H01F27/29 ,  H01F17/00 ,  H01F17/04

Abstract: A coil component includes: a body including a magnetic material, coil pattern layers disposed in the magnetic material, a core portion surrounded by the coil pattern layers, and an insulating layer disposed in the core portion and between adjacent coil pattern layers among the coil pattern layers, wherein each of the coil pattern layers comprises a spiral-shaped pattern; and an external electrode disposed on the body.

公开(公告)号：US10811328B1

公开(公告)日：2020-10-20

申请号：US16513193

申请日：2019-07-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Myung Sam Kang ,  Moon Il Kim ,  Young Gwan Ko

IPC: H01L23/055 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package may include a frame including an insulation layer having a cavity formed in a lower surface of the insulation layer, a first post and a second post spaced apart from the cavity, and a metal plate disposed on an upper side of the cavity; a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposing the first surface; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the frame and the first surface of the semiconductor chip, and including one or more redistribution layers. The first post is electrically connected to the wiring layer of the frame and the redistribution layer of the connection structure, and the second post is spaced apart from the first post.