公开(公告)号：US20140070410A1

公开(公告)日：2014-03-13

申请号：US14084745

申请日：2013-11-20

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

Abstract translation: 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。

公开(公告)号：US09524958B2

公开(公告)日：2016-12-20

申请号：US13928862

申请日：2013-06-27

Applicant: STATS ChipPAC, Ltd.

Inventor： JoonYoung Choi ,  YongHee Kang ,  HunTeak Lee ,  KeonTaek Kang ,  YoungChul Kim

IPC: H01L21/76 ,  H01L29/24 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.

Abstract translation: 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。

公开(公告)号：US20150001703A1

公开(公告)日：2015-01-01

申请号：US13928862

申请日：2013-06-27

Applicant: STATS ChipPAC, Ltd.

Inventor： JoonYoung Choi ,  YongHee Kang ,  HunTeak Lee ,  KeonTaek Kang ,  YoungChul Kim

IPC: H01L25/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a carrier with an interface layer applied over the carrier. The interface layer can include non-conductive paste or non-conductive film. A plurality of semiconductor die is mounted to the carrier and interface layer by pressing the semiconductor die to the carrier and interface layer for one second or less, and simultaneously thermal compression bonding multiple semiconductor die to the carrier and interface layer for 5-10 seconds. By pressing the semiconductor die to the interface layer for a short period of time and then simultaneously thermal compression bonding multiple semiconductor die to the interface layer for a second longer period of time, the overall throughput of die bonding increases to process more die per unit of time. An encapsulant is deposited over the semiconductor die. The carrier is removed and interconnect structure is formed over the semiconductor die and encapsulant.

Abstract translation: 半导体器件包括具有施加在载体上的界面层的载体。 界面层可以包括非导电浆料或非导电膜。 将多个半导体管芯通过将半导体管芯压入载体和界面层1秒以下，同时将多个半导体管芯与载体和界面层热粘合5-10秒，从而安装在载体和界面层上。 通过将半导体管芯压入界面层一段较短的时间，然后同时将多个半导体管芯同时热压粘合到界面层上较长的时间段，芯片接合的总体生产量增加，以处理更多的单位 时间。 密封剂沉积在半导体管芯上。 移除载体并且在半导体管芯和密封剂上形成互连结构。

公开(公告)号：US09780063B2

公开(公告)日：2017-10-03

申请号：US14328922

申请日：2014-07-11

Applicant: STATS ChipPAC, Ltd.

Inventor： JoonYoung Choi ,  YoungJoon Kim ,  SungWon Cho

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

公开(公告)号：US09252093B2

公开(公告)日：2016-02-02

申请号：US14084745

申请日：2013-11-20

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  JoonYoung Choi ,  Wonll Kwon

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

Abstract: A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

Abstract translation: 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。

公开(公告)号：US20140319680A1

公开(公告)日：2014-10-30

申请号：US14328922

申请日：2014-07-11

Applicant: STATS ChipPAC, Ltd.

Inventor： JoonYoung Choi ,  YoungJoon Kim ,  SungWon Cho

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Abstract translation: 半导体晶片具有多个具有用于电互连的接触焊盘的半导体管芯。 在半导体晶片上形成绝缘层。 在接触焊盘上形成凸块结构。 凸块结构具有形成在绝缘层和接触垫上的缓冲层。 去除缓冲层的一部分以暴露接触焊盘和绝缘层的外部部分。 在缓冲层和接触垫上形成UBM层。 UBM层遵循缓冲层和接触垫的轮廓。 使用填充有导电材料的图案化光致抗蚀剂层在UBM层之上形成环形导电柱。 导电阻挡层形成在环形导电柱上。 在导电阻挡层上形成凸块。 缓冲层减少凸块和接触垫上的热应力和机械应力。