公开(公告)号：US10338876B2

公开(公告)日：2019-07-02

申请号：US15333692

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Youn Kim ,  Hyun Seong Kum ,  Young Hwan Park

IPC: G06F3/14 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1368 ,  G09G3/34 ,  H01L25/075 ,  H01L27/32 ,  H01L33/50 ,  H01L33/54 ,  H01L33/62 ,  G02F1/1339 ,  G02F1/1362 ,  G09G3/3225 ,  G09G3/36 ,  H01L27/12

Abstract: A multivision apparatus may include a display panel that includes a display screen including a first region and an adjacent second region. The first region may include first pixels, and the second region may include second pixels. The first pixels and the second pixels have different structures. The display panel may display a single image across the first region and the second region of the display screen. The multivision apparatus may include an array of interconnected display panels configured to collectively display an image, based on each given display panel displaying a separate sub-image in the first and second regions of the given display panel.

公开(公告)号：US09525106B2

公开(公告)日：2016-12-20

申请号：US14676750

申请日：2015-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Sun Maeng ,  Jun Youn Kim ,  Sung Min Choi ,  Kyung Ho Yoo

IPC: H01L29/06 ,  H01L33/32 ,  H01L33/06 ,  H01L33/14

CPC classification number: H01L33/325 ,  H01L33/06 ,  H01L33/145

Abstract: A semiconductor light emitting device includes: an n-type semiconductor layer and a p-type semiconductor layer; an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer; and an electron blocking layer disposed between the active layer and the p-type semiconductor layer and doped with a p-type dopant element. The electron blocking layer is formed of AlxGa1-xN, where 0

Abstract translation: 半导体发光器件包括：n型半导体层和p型半导体层; 设置在n型半导体层和p型半导体层之间的有源层; 以及设置在有源层和p型半导体层之间并掺杂有p型掺杂元素的电子阻挡层。 电子阻挡层由Al x Ga 1-x N形成，其中0

公开(公告)号：US09947530B2

公开(公告)日：2018-04-17

申请号：US15399898

申请日：2017-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jo Tak ,  Sam Mook Kang ,  Mi Hyun Kim ,  Jun Youn Kim ,  Young Soo Park

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/304 ,  H01L21/30604

Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.

公开(公告)号：US09899565B2

公开(公告)日：2018-02-20

申请号：US15183869

申请日：2016-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jo Tak ,  Sam Mook Kang ,  Mi Hyun Kim ,  Jun Youn Kim ,  Young Soo Park ,  Misaichi Takeuchi

IPC: H01L33/00 ,  H01L21/683 ,  H01L21/306 ,  H01L21/78 ,  H01L21/02

CPC classification number: H01L33/0075 ,  H01L21/02005 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/7806 ,  H01L33/0066 ,  H01L33/0079

Abstract: A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.

公开(公告)号：US10600645B2

公开(公告)日：2020-03-24

申请号：US15662425

申请日：2017-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mi Hyun Kim ,  Sam Mook Kang ,  Jun Youn Kim ,  Young Jo Tak

IPC: H01L21/02 ,  C30B25/18 ,  C30B25/04 ,  C30B25/02 ,  C30B29/40 ,  H01L21/78 ,  B08B3/02 ,  B08B3/12

Abstract: A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

公开(公告)号：US09666754B2

公开(公告)日：2017-05-30

申请号：US15130379

申请日：2016-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Hwan Park ,  Sam Mook Kang ,  Jun Youn Kim ,  Mi Hyun Kim ,  Joo Sung Kim ,  Young Jo Tak

IPC: H01L21/30 ,  H01L21/46 ,  H01L33/00 ,  H01L33/12

CPC classification number: H01L33/007 ,  F21K9/237 ,  F21K9/275 ,  F21S41/141 ,  F21S43/14 ,  F21V23/005 ,  F21Y2113/10 ,  F21Y2115/10 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L33/12 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor substrate may include: forming a buffer layer on a growth substrate; forming a plurality of openings in the buffer layer, the plurality of openings penetrating through the buffer layer and being spaced apart from one another; forming a plurality of cavities on the growth substrate, the plurality of cavities being aligned to respectively correspond to the plurality of openings; growing a semiconductor layer on the buffer layer, the growing the semiconductor layer including filling the plurality of openings with the semiconductor layer; and separating the buffer layer and the semiconductor layer from the growth substrate, wherein a diameter of each of the plurality of openings at a boundary between the growth substrate and the buffer layer is smaller than a diameter of each of the plurality of cavities at the boundary.