公开(公告)号：US09136260B2

公开(公告)日：2015-09-15

申请号：US14093853

申请日：2013-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC: H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768 ,  H01L21/683 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。

公开(公告)号：US20150221517A1

公开(公告)日：2015-08-06

申请号：US14613822

申请日：2015-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-mi Kim ,  Un-byoung Kang ,  Tae-je Cho ,  Jung-seok Ahn

IPC: H01L21/306 ,  H01L21/768 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L21/304 ,  C09J7/22 ,  C09J7/30 ,  C09J2201/36 ,  C09J2203/326 ,  C09J2433/00 ,  C09J2463/00 ,  H01L21/30604 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/03 ,  H01L24/06 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device capable of thinning a semiconductor chip can be performed while preventing the semiconductor chip from being damaged. A method of manufacturing a semiconductor device includes: preparing a semiconductor substrate including a plurality of semiconductor chips, attaching the semiconductor substrate to a support substrate with an adhesive support film, removing an edge region of the semiconductor substrate together with a portion of the adhesive support film between the edge region of the semiconductor substrate and the support substrate and, thereafter, polishing the semiconductor substrate to thin the semiconductor substrate.

Abstract translation: 可以在防止半导体芯片损坏的同时进行制造能够使半导体芯片变薄的半导体器件的制造方法。 一种制造半导体器件的方法包括：制备包括多个半导体芯片的半导体衬底，用粘合剂支撑膜将半导体衬底附着到支撑衬底上，与粘合剂支撑体的一部分一起去除半导体衬底的边缘区域 在半导体衬底的边缘区域和支撑衬底之间形成薄膜，然后对半导体衬底进行抛光以使半导体衬底变薄。

公开(公告)号：US09412707B2

公开(公告)日：2016-08-09

申请号：US14702662

申请日：2015-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-soo Chung ,  Tae-je Cho ,  Jung-seok Ahn ,  In-young Lee

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/78 ,  H01L21/304 ,  H01L21/683 ,  H01L25/00 ,  H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/4803 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.

Abstract translation: 本发明的实施例包括一种制造半导体封装的方法，该半导体封装包括多个层叠半导体芯片，其中半导体封装在晶片级制造时可以防止半导体晶片衬底的边缘损坏或破裂，而直径 的模制元件的直径大于半导体晶片衬底的直径。 成型元件可以覆盖晶片基板的表面和多个堆叠的半导体芯片。 实施例可以包括晶片级半导体封装，其包括具有第一直径的圆形衬底，附着到圆形衬底的圆形钝化层，具有第一直径的钝化层和覆盖多个半导体芯片的表面的圆形模制元件，以及 覆盖基板的有效区域。 圆形模制元件可以具有大于第一直径的第二直径。