公开(公告)号：US08643070B2

公开(公告)日：2014-02-04

申请号：US13314122

申请日：2011-12-07

申请人： Shu-Ming Chang ,  Chien-Hui Chen ,  Yen-Shih Ho ,  Chien-Hung Liu ,  Ho-Yin Yiu ,  Ying-Nan Wen

发明人： Shu-Ming Chang ,  Chien-Hui Chen ,  Yen-Shih Ho ,  Chien-Hung Liu ,  Ho-Yin Yiu ,  Ying-Nan Wen

IPC分类号： H01L29/76

CPC分类号： H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

摘要： An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有第一表面和相对的第二表面的半导体衬底; 位于半导体衬底中的漏区; 源区域，位于所述半导体衬底中; 位于所述半导体衬底上或者至少部分地埋在所述半导体衬底中的栅极，其中栅极电介质层位于所述栅极和所述半导体衬底之间; 漏极导电结构，设置在所述半导体衬底的所述第一表面上并电连接到所述漏极区; 源极导电结构，其设置在所述半导体衬底的所述第二表面上并电连接到所述源极区; 以及栅极导电结构，其设置在所述半导体衬底的所述第一表面上并电连接到所述栅极。

公开(公告)号：US09024437B2

公开(公告)日：2015-05-05

申请号：US13524985

申请日：2012-06-15

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L23/48 ,  H01L21/78 ,  H01L23/31

CPC分类号： H01L23/3128 ,  H01L23/3114 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1461 ,  H01L2924/014 ,  H01L2924/00

摘要： An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括：具有多个侧面和多个拐角区域的基板，其中每个所述拐角区域位于所述基板的至少两个侧面的相交处; 形成在所述基板中的器件区域; 导电层，其设置在所述基板上并电连接到所述器件区域; 设置在所述基板和所述导电层之间的绝缘层; 以及载体基板，其中所述基板设置在所述载体基板上，并且所述基板具有在至少一个所述拐角区域中朝向所述载体基板延伸的凹部。

公开(公告)号：US09711403B2

公开(公告)日：2017-07-18

申请号：US13352234

申请日：2012-01-17

申请人： Chien-Hui Chen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Yen-Shih Ho

发明人： Chien-Hui Chen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC分类号： H01L21/78 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

摘要： An embodiment of the invention provides a method for forming a chip package which includes: providing a substrate having a first surface and a second surface, wherein at least two conducting pads are disposed on the first surface of the substrate; partially removing the substrate from the second surface of the substrate to form at least two holes extending towards the first surface, wherein the holes correspondingly and respectively align with one of the conducting pads; after the holes are formed, partially removing the substrate from the second substrate to form at least a recess extending towards the first surface, wherein the recess overlaps with the holes; forming an insulating layer on a sidewall and a bottom of the trench and on sidewalls of the holes; and forming a conducting layer on the insulating layer, wherein the conducting layer electrically contacts with one of the conducting pads.

公开(公告)号：US08836134B2

公开(公告)日：2014-09-16

申请号：US13738082

申请日：2013-01-10

申请人： Po-Shen Lin ,  Chuan-Jin Shiu ,  Bing-Siang Chen ,  Chen-Han Chiang ,  Chien-Hui Chen ,  Hsi-Chien Lin ,  Yen-Shih Ho

发明人： Po-Shen Lin ,  Chuan-Jin Shiu ,  Bing-Siang Chen ,  Chen-Han Chiang ,  Chien-Hui Chen ,  Hsi-Chien Lin ,  Yen-Shih Ho

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L21/78 ,  B81C1/00888 ,  H01L21/561 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/562 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/16235 ,  H01L2924/00

摘要： A method of fabricating a semiconductor stacked package is provided. A singulation process is performed on a wafer and a substrate, on which the wafer is stacked. A portion of the wafer on a cutting region is removed, to form a stress concentrated region on an edge of a chip of the wafer. The wafer and the substrate are then cut, and a stress is forced to be concentrated on the edge of the chip of the wafer. As a result, the edge of the chip is warpaged. Therefore, the stress is prevented from extending to the inside of the chip. A semiconductor stacked package is also provided.

摘要翻译： 提供一种制造半导体堆叠封装的方法。 在晶片和基板上进行单晶化处理，晶片和晶片被堆叠在其上。 去除切割区域上的晶片的一部分，以在晶片的芯片的边缘上形成应力集中区域。 然后切割晶片和基板，并且迫使应力集中在晶片的芯片的边缘上。 结果，芯片的边缘变形。 因此，防止了应力延伸到芯片的内部。 还提供半导体堆叠封装。

公开(公告)号：US08558262B2

公开(公告)日：2013-10-15

申请号：US13024337

申请日：2011-02-10

申请人： Shang-Yi Wu ,  Chien-Hui Chen

发明人： Shang-Yi Wu ,  Chien-Hui Chen

IPC分类号： H01L33/00

CPC分类号： H01L33/60 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L33/44 ,  H01L33/486 ,  H01L33/62 ,  H01L33/641 ,  H01L2224/73265 ,  H01L2933/0033 ,  H01S5/02236 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A method for fabricating a silicon submount for LED packaging. A silicon substrate is provided. A reflection layer is formed on the silicon substrate. Portions of the reflection layer and the silicon substrate are removed to form openings. A wafer backside grinding process is carried out to thin the silicon substrate thereby turning the openings into through silicon vias. An insulating layer is then deposited to cover the reflection layer and the silicon substrate. A seed layer is formed on the insulating layer. A resist pattern is then formed on the seed layer. A metal layer is formed on the seed layer not covered by the resist pattern. The resist pattern is then stripped. The seed layer not covered by the metal layer is then removed.

摘要翻译： 一种用于制造用于LED封装的硅基座的方法。 提供硅衬底。 在硅衬底上形成反射层。 去除反射层和硅衬底的部分以形成开口。 进行晶片背面研磨处理以使硅衬底变薄，从而将开口转变成通过硅通孔。 然后沉积绝缘层以覆盖反射层和硅衬底。 种子层形成在绝缘层上。 然后在种子层上形成抗蚀剂图案。 在未被抗蚀剂图案覆盖的种子层上形成金属层。 然后剥离抗蚀剂图案。 然后除去未被金属层覆盖的籽晶层。

公开(公告)号：US08698316B2

公开(公告)日：2014-04-15

申请号：US13190408

申请日：2011-07-25

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68377 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电焊盘; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的侧壁基本上垂直于所述衬底的下表面，并且所述孔的侧壁或所述底部露出所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08525345B2

公开(公告)日：2013-09-03

申请号：US13044457

申请日：2011-03-09

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located in the substrate or under the lower surface thereof, a dielectric layer located between the conducting pads, a hole extending from the upper surface towards the lower surface of the substrate and exposing a portion of the conducting pads, and a conducting layer located in the hole and electrically contacting the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括具有上表面和下表面的衬底，位于衬底中或其下表面下方的多个导电焊盘，位于导电焊盘之间的介电层，从上表面向下延伸的孔 表面并暴露一部分导电焊盘，以及导电层，其位于孔中并与导电焊盘电接触。

公开(公告)号：US08878367B2

公开(公告)日：2014-11-04

申请号：US13303208

申请日：2011-11-23

申请人： Chia-Sheng Lin ,  Chien-Hui Chen ,  Bing-Siang Chen ,  Tzu-Hsiang Hung

发明人： Chia-Sheng Lin ,  Chien-Hui Chen ,  Bing-Siang Chen ,  Tzu-Hsiang Hung

IPC分类号： H01L23/538 ,  H01L21/50 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76898 ,  H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate structure with through vias is provided. The substrate structure with through vias includes a semiconductor substrate having a back surface and a via penetrating the back surface, a metal layer, a first insulating layer and a second insulating layer. The first insulating layer is formed on the back surface of the semiconductor substrate and has an opening connected to the through via. The second insulating layer is formed on the first insulating layer and has a portion extending into the opening and the via to form a trench insulating layer. The bottom of the trench insulating layer is etched back to form a footing portion at the corner of the via. The footing portion has a height less than a total height of the first and second insulating layers.

摘要翻译： 提供具有通孔的衬底结构。 具有贯通孔的衬底结构包括具有后表面和穿过背面的通孔的半导体衬底，金属层，第一绝缘层和第二绝缘层。 第一绝缘层形成在半导体衬底的后表面上，并且具有连接到通孔的开口。 第二绝缘层形成在第一绝缘层上，并且具有延伸到开口中的部分和通孔以形成沟槽绝缘层。 沟槽绝缘层的底部被回蚀以在通孔的拐角处形成基部。 所述基脚部分的高度小于所述第一和第二绝缘层的总高度。

公开(公告)号：US08692382B2

公开(公告)日：2014-04-08

申请号：US13190388

申请日：2011-07-25

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  B81B7/007 ,  B81B2207/07 ,  B81B2207/092 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/3178 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/9202 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/00

摘要： According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein an upper sidewall of the hole inclines to the lower surface of the substrate, and a lower sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads.

摘要翻译： 根据本发明的实施例，提供了芯片封装。 芯片封装包括：具有上表面和下表面的基板; 位于所述基板的下表面下方的多个导电垫; 位于导电垫之间的电介质层; 从衬底的上表面延伸到下表面的沟槽; 从所述沟槽的底部延伸到所述衬底的下表面的孔，其中所述孔的上侧壁倾斜到所述衬底的下表面，并且所述孔的下侧壁或底部暴露所述导电垫的一部分 ; 以及导电层，其位于所述孔中并电连接到至少一个所述导电焊盘。

公开(公告)号：US08552565B2

公开(公告)日：2013-10-08

申请号：US13204603

申请日：2011-08-05

申请人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

发明人： Yu-Lin Yen ,  Chien-Hui Chen ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/561 ,  H01L21/76805 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/06 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/05552

摘要： A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.

摘要翻译： 芯片封装包括具有上表面和下表面的衬底，位于衬底的下表面下方的多个导电衬垫以及位于导电焊盘之间的电介质层。 在衬底中设置有一个孔，该孔从衬底的上表面向下表面延伸。 孔的侧壁或底部暴露出导电垫的一部分。 上表面附近的孔的上部开口小于靠近下表面的孔的下部开口。 上导电焊盘至少具有暴露导电焊盘的下导电焊盘的开口或沟槽。 导电层设置在孔中，该导电层与至少一个导电垫电接触。