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公开(公告)号:US08643070B2
公开(公告)日:2014-02-04
申请号:US13314122
申请日:2011-12-07
申请人: Shu-Ming Chang , Chien-Hui Chen , Yen-Shih Ho , Chien-Hung Liu , Ho-Yin Yiu , Ying-Nan Wen
发明人: Shu-Ming Chang , Chien-Hui Chen , Yen-Shih Ho , Chien-Hung Liu , Ho-Yin Yiu , Ying-Nan Wen
IPC分类号: H01L29/76
CPC分类号: H01L24/05 , H01L21/6835 , H01L21/76898 , H01L24/03 , H01L2221/6834 , H01L2221/6835 , H01L2221/68368 , H01L2224/0401 , H01L2224/05558 , H01L2224/05572 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/014 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a drain region located in the semiconductor substrate; a source region located in the semiconductor substrate; a gate located on the semiconductor substrate or at least partially buried in the semiconductor substrate, wherein a gate dielectric layer is between the gate and the semiconductor substrate; a drain conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the drain region; a source conducting structure disposed on the second surface of the semiconductor substrate and electrically connected to the source region; and a gate conducting structure disposed on the first surface of the semiconductor substrate and electrically connected to the gate.
摘要翻译: 本发明的实施例提供一种芯片封装,其包括:具有第一表面和相对的第二表面的半导体衬底; 位于半导体衬底中的漏区; 源区域,位于所述半导体衬底中; 位于所述半导体衬底上或者至少部分地埋在所述半导体衬底中的栅极,其中栅极电介质层位于所述栅极和所述半导体衬底之间; 漏极导电结构,设置在所述半导体衬底的所述第一表面上并电连接到所述漏极区; 源极导电结构,其设置在所述半导体衬底的所述第二表面上并电连接到所述源极区; 以及栅极导电结构,其设置在所述半导体衬底的所述第一表面上并电连接到所述栅极。
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公开(公告)号:US08614488B2
公开(公告)日:2013-12-24
申请号:US13314114
申请日:2011-12-07
申请人: Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
发明人: Ying-Nan Wen , Ho-Yin Yiu , Yen-Shih Ho , Shu-Ming Chang , Chien-Hung Liu , Shih-Yi Lee , Wei-Chung Yang
IPC分类号: H01L21/70
CPC分类号: H01L21/76898 , H01L21/6835 , H01L23/3114 , H01L23/3185 , H01L23/481 , H01L24/05 , H01L24/13 , H01L2221/68327 , H01L2221/6834 , H01L2221/6835 , H01L2221/68363 , H01L2224/02372 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05567 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05666 , H01L2224/05669 , H01L2224/05672 , H01L2224/11002 , H01L2224/13007 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/96 , H01L2924/00013 , H01L2924/00014 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/014 , H01L2224/03 , H01L2224/11 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要: A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.
摘要翻译: 芯片封装包括:基板; 位于衬底中的漏极和源极区域; 位于衬底上或埋在衬底中的门; 漏极导电结构,源极导电结构和栅极导电结构,分别设置在所述衬底上并电连接到所述漏极区域,所述源极区域和所述栅极; 设置在所述基板旁边的第二基板; 位于所述第二基板中的第二漏极和第二源极区域,其中所述第二漏极区域电连接到所述源极区域; 位于第二基板上或埋在第二基板中的第二栅极; 以及第二源极和第二栅极导电结构,其设置在所述第二基板上并分别电连接到所述第二源极区域和所述第二栅极,其中所述漏极,所述源极,所述栅极,所述第二源极和所述第二栅极的端点 栅极导电结构基本上共面。
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公开(公告)号:US08981497B2
公开(公告)日:2015-03-17
申请号:US13548663
申请日:2012-07-13
申请人: Ho-Yin Yiu , Chien-Hung Liu , Tsang-Yu Liu , Ying-Nan Wen , Yen-Shih Ho
发明人: Ho-Yin Yiu , Chien-Hung Liu , Tsang-Yu Liu , Ying-Nan Wen , Yen-Shih Ho
IPC分类号: H01L27/14 , H01L29/82 , H01L29/84 , B81B3/00 , H01L27/146
CPC分类号: B81B3/0051 , B81B2201/025 , H01L27/14618 , H01L2924/0002 , H01L2924/00
摘要: A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.
摘要翻译: 公开了一种用于形成芯片封装结构的芯片封装结构和方法。 至少一个块形成在盖的表面上,盖安装在其上形成有感测装置的基板上,用于覆盖感测装置,并且该块设置在盖和感测装置之间。 在本发明中,该块安装在盖上,不需要蚀刻盖以形成突出部分,因此本发明的方法简单且成本低。
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公开(公告)号:US20130020693A1
公开(公告)日:2013-01-24
申请号:US13548663
申请日:2012-07-13
申请人: Ho-Yin Yiu , Chien-Hung Liu , Tsang-Yu Liu , Ying-Nan Wen , Yen-Shih Ho
发明人: Ho-Yin Yiu , Chien-Hung Liu , Tsang-Yu Liu , Ying-Nan Wen , Yen-Shih Ho
CPC分类号: B81B3/0051 , B81B2201/025 , H01L27/14618 , H01L2924/0002 , H01L2924/00
摘要: A chip package structure and a method for forming the chip package structure are disclosed. At least a block is formed on a surface of a cover, the cover is mounted on a substrate having a sensing device formed thereon for covering the sensing device, and the block is disposed between the cover and the sensing device. In the present invention, the block is mounted on the cover, there is no need to etch the cover to form a protruding portion, and thus the method of the present invention is simple and has low cost.
摘要翻译: 公开了一种用于形成芯片封装结构的芯片封装结构和方法。 至少一个块形成在盖的表面上,盖安装在其上形成有感测装置的基板上,用于覆盖感测装置,并且该块设置在盖和感测装置之间。 在本发明中,该块安装在盖上,不需要蚀刻盖以形成突出部分,因此本发明的方法简单且成本低。
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公开(公告)号:US08791768B2
公开(公告)日:2014-07-29
申请号:US13359460
申请日:2012-01-26
申请人: Ho-Yin Yiu , Chien-Hung Liu , Ying-Nan Wen , Shih-Yi Lee , Wei-Chung Yang , Bai-Yao Lou , Hung-Jen Lee
发明人: Ho-Yin Yiu , Chien-Hung Liu , Ying-Nan Wen , Shih-Yi Lee , Wei-Chung Yang , Bai-Yao Lou , Hung-Jen Lee
CPC分类号: H01L23/642 , H01L23/48 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/13101 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49175 , H01L2924/00014 , H01L2924/01327 , H01L2924/1901 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2924/014
摘要: Embodiments of the present invention provide a capacitive coupler packaging structure including a substrate with at least one capacitor and a receiver formed thereon, wherein the at least one capacitor at least includes a first electrode layer, a second electrode layer and a capacitor dielectric layer therebetween, and the first electrode layer is electrically connected to the receiver via a solder ball. The capacitive coupler packaging structure also includes a transmitter electrically connecting to the capacitor.
摘要翻译: 本发明的实施例提供一种电容耦合器封装结构,其包括具有至少一个电容器的基板和形成在其上的接收器,其中所述至少一个电容器至少包括第一电极层,第二电极层和电介质层之间, 并且第一电极层通过焊球电连接到接收器。 电容耦合器封装结构还包括电连接到电容器的发射器。
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公开(公告)号:US20110233782A1
公开(公告)日:2011-09-29
申请号:US13052769
申请日:2011-03-21
申请人: Shu-Ming CHANG , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
发明人: Shu-Ming CHANG , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
CPC分类号: H01L21/50 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/32 , H01L24/81 , H01L24/92 , H01L24/93 , H01L24/94 , H01L33/62 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02371 , H01L2224/0239 , H01L2224/024 , H01L2224/0346 , H01L2224/0347 , H01L2224/03825 , H01L2224/039 , H01L2224/0391 , H01L2224/0401 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/1146 , H01L2224/1147 , H01L2224/11825 , H01L2224/119 , H01L2224/1191 , H01L2224/13021 , H01L2224/13024 , H01L2224/131 , H01L2224/136 , H01L2224/16225 , H01L2224/32052 , H01L2224/32225 , H01L2224/32245 , H01L2224/81191 , H01L2224/81192 , H01L2224/92142 , H01L2224/92143 , H01L2224/93 , H01L2224/94 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2224/0231 , H01L2224/11 , H01L2224/1182 , H01L2224/03 , H01L2224/0382 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.
摘要翻译: 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片,其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。
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公开(公告)号:US08710680B2
公开(公告)日:2014-04-29
申请号:US13052769
申请日:2011-03-21
申请人: Shu-Ming Chang , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
发明人: Shu-Ming Chang , Bai-Yao Lou , Ying-Nan Wen , Chien-Hung Liu
IPC分类号: H01L29/40
CPC分类号: H01L21/50 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/32 , H01L24/81 , H01L24/92 , H01L24/93 , H01L24/94 , H01L33/62 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02371 , H01L2224/0239 , H01L2224/024 , H01L2224/0346 , H01L2224/0347 , H01L2224/03825 , H01L2224/039 , H01L2224/0391 , H01L2224/0401 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/1146 , H01L2224/1147 , H01L2224/11825 , H01L2224/119 , H01L2224/1191 , H01L2224/13021 , H01L2224/13024 , H01L2224/131 , H01L2224/136 , H01L2224/16225 , H01L2224/32052 , H01L2224/32225 , H01L2224/32245 , H01L2224/81191 , H01L2224/81192 , H01L2224/92142 , H01L2224/92143 , H01L2224/93 , H01L2224/94 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2224/0231 , H01L2224/11 , H01L2224/1182 , H01L2224/03 , H01L2224/0382 , H01L2224/81 , H01L2224/83 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要: An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed.
摘要翻译: 公开了一种电子器件封装。 该封装包括至少一个具有第一表面和与其相对的第二表面的半导体芯片,其中至少一个再分配层设置在半导体芯片的第一表面上并与至少一个导电焊盘结构电连接。 至少一个邻接部分设置在再分布层上并与其电接触。 钝化层覆盖半导体芯片的第一表面并围绕邻接部分。 将衬底附着到半导体芯片的第二表面上。 还公开了一种电子器件封装的制造方法。
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公开(公告)号:US09088206B2
公开(公告)日:2015-07-21
申请号:US13359466
申请日:2012-01-26
申请人: Ho-Yin Yiu , Chien-Hung Liu , Wei-Chung Yang , Bai-Yao Lou
发明人: Ho-Yin Yiu , Chien-Hung Liu , Wei-Chung Yang , Bai-Yao Lou
IPC分类号: H01L29/06 , H01L27/06 , H04B1/02 , H02M3/155 , H02M3/00 , H01F17/00 , H01L23/64 , H01L25/16 , H01L23/00 , H01L25/07
CPC分类号: H02M3/155 , H01F17/0006 , H01F2017/0046 , H01F2017/0073 , H01F2017/0086 , H01L23/645 , H01L24/16 , H01L25/072 , H01L25/165 , H01L2224/16225 , H01L2924/13091 , H01L2924/16195 , H01L2924/19105 , H02M3/00
摘要: A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.
摘要翻译: 电源模块包括基板; 形成在具有特定图案的基板上的导电路径层作为电感器; 连接层形成在所述基板上并电连接到所述电感器的第一端子; 以及第一晶体管,通过连接层电安装在基板上。
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公开(公告)号:US08692284B2
公开(公告)日:2014-04-08
申请号:US13484140
申请日:2012-05-30
申请人: Ying-Nan Wen , Chien-Hung Liu , Wei-Chung Yang
发明人: Ying-Nan Wen , Chien-Hung Liu , Wei-Chung Yang
IPC分类号: H01L29/72
CPC分类号: H05K3/185 , H01L2224/48091 , H01L2224/48227 , H01L2924/1461 , H01L2924/181 , H05K1/115 , H05K3/0023 , H05K3/426 , H05K2201/10378 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要: An embodiment of the present invention provides a manufacturing method of an interposer including: providing a semiconductor substrate having a first surface, a second surface and at least a through hole connecting the first surface to the second surface; electrocoating a polymer layer on the first surface, the second surface and an inner wall of the through hole; and forming a wiring layer on the electrocoating polymer layer, wherein the wiring layer extends from the first surface to the second surface via the inner wall of the through hole. Another embodiment of the present invention provides an interposer.
摘要翻译: 本发明的一个实施例提供了一种内插器的制造方法,包括:提供具有第一表面,第二表面和至少连接第一表面与第二表面的通孔的半导体衬底; 在第一表面,第二表面和通孔的内壁上电聚合聚合物层; 以及在所述电涂层聚合物层上形成布线层,其中所述布线层经由所述通孔的内壁从所述第一表面延伸到所述第二表面。 本发明的另一实施例提供一种插入器。
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公开(公告)号:US08823179B2
公开(公告)日:2014-09-02
申请号:US12667383
申请日:2008-06-13
申请人: Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
发明人: Chia-Lun Tsai , Wen-Cheng Chien , Po-Han Lee , Wei-Ming Chen , Chien-Hung Liu , Ying-Nan Wen
IPC分类号: H01L23/48 , H01L27/146 , H01L21/768 , H01L23/00
CPC分类号: H01L23/481 , H01L21/76898 , H01L24/12 , H01L27/14618 , H01L27/14683 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05624 , H01L2224/05639 , H01L2224/05655 , H01L2924/00014 , H01L2924/01021 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/3025 , H01L2924/00 , H01L2224/05099
摘要: An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.
摘要翻译: 本发明的实施例提供了一种电子器件封装,其包括具有第一表面和相对的第二表面的芯片以及沿着从第二表面到第一表面的方向延伸到芯片的主体中的沟槽,其中底部 沟槽的一部分包括至少两个接触孔。
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