公开(公告)号：US11600562B2

公开(公告)日：2023-03-07

申请号：US17075700

申请日：2020-10-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Jung Tseng ,  Fu-Jen Li

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes an interposer, a die, a protective layer, a plurality of first electrical connectors and a first molding material. The die includes a first surface and a second surface opposite to the first surface, and the die is bonded to the interposer through the first surface. The protective layer is disposed on the second surface of the die. The first electrical connectors are disposed aside the die. The first molding material is disposed aside the die, the protection layer and the first electrical connectors.

公开(公告)号：US09515038B2

公开(公告)日：2016-12-06

申请号：US14704563

申请日：2015-05-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Chia-Jen Cheng ,  Hsiu-Mei Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L21/76885 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/82 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10155 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/207 ,  H01L2924/2076 ,  H01L2224/05552

Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

公开(公告)号：US09502387B2

公开(公告)日：2016-11-22

申请号：US14990547

申请日：2016-01-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H05K1/11 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H05K1/02 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H05K1/0271 ,  H05K1/11 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10613 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.

公开(公告)号：US20150041987A1

公开(公告)日：2015-02-12

申请号：US13961589

申请日：2013-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Wen-Yi Lin ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L23/48 ,  H01L23/28 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.

Abstract translation: 本公开的实施例包括半导体器件，封装以及形成半导体器件和封装的方法。 一个实施例是一种半导体器件，其包括在第一衬底上的模制材料，第一开口具有在模制材料中的第一宽度。 所述半导体器件还包括第二开口，所述第二开口在所述模制材料中具有第二宽度，所述第二宽度大于所述第一宽度。 第一连接器位于第一开口中，第二连接器位于第二开口中。

公开(公告)号：US08901732B2

公开(公告)日：2014-12-02

申请号：US13796610

申请日：2013-03-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Wen-Yi Lin ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L23/04 ,  H01L21/48 ,  H01L23/36 ,  H01L21/56 ,  H01L21/50 ,  H01L23/373 ,  H01L23/367

CPC classification number: H01L23/04 ,  H01L21/4871 ,  H01L21/50 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Various packages and methods are disclosed. A package according to an embodiment includes a substrate, a chip attached to a surface of the substrate with electrical connectors, a molding compound on the surface of the substrate and around the chip, an adhesive on a surface of the chip that is distal from the surface of the substrate, and a lid on the adhesive. In an embodiment, a region between the molding compound and the lid at a corner of the lid is free from the adhesive. In another embodiment, the lid has a recess in a surface of the lid facing the surface of the molding compound.

Abstract translation: 公开了各种包装和方法。 根据一个实施方案的包装包括基材，附着到具有电连接器的基材表面上的芯片，在基材表面上和芯片周围的模塑料，芯片表面上的粘合剂，其远离 基板的表面和粘合剂上的盖。 在一个实施例中，模制化合物和盖的角落处的盖之间的区域不含粘合剂。 在另一个实施例中，盖子在盖子的面对模塑料的表面的表面上具有凹槽。

公开(公告)号：US20240371745A1

公开(公告)日：2024-11-07

申请号：US18770618

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Jung Tseng ,  Fu-Jen Li

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a first interconnect substrate, a first die and a first encapsulant. The first interconnect substrate includes a plurality of first conductive connectors thereon. The first die is bonded to the first interconnect substrate and has a protective layer thereon. The first encapsulant encapsulates the first conductive connectors, the first die and the protective layer.

公开(公告)号：US09252076B2

公开(公告)日：2016-02-02

申请号：US13961589

申请日：2013-08-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Wen-Yi Lin ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81484 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.

Abstract translation: 本公开的实施例包括半导体器件，封装以及形成半导体器件和封装的方法。 一个实施例是一种半导体器件，其包括在第一衬底上的模制材料，第一开口具有在模制材料中的第一宽度。 所述半导体器件还包括第二开口，所述第二开口在所述模制材料中具有第二宽度，所述第二宽度大于所述第一宽度。 第一连接器位于第一开口中，第二连接器位于第二开口中。

公开(公告)号：US09087882B2

公开(公告)日：2015-07-21

申请号：US14141734

申请日：2013-12-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Chia-Jen Cheng ,  Hsiu-Mei Yu

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/76885 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/82 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10155 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/207 ,  H01L2924/2076 ,  H01L2224/05552

Abstract: A system and method for providing a post-passivation and underbump metallization is provided. An embodiment comprises a post-passivation layer that is larger than an overlying underbump metallization. The post-passivation layer extending beyond the underbump metallization shields the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.

Abstract translation: 提供了一种用于提供后钝化和欠掺杂金属化的系统和方法。 一个实施例包括大于上覆下凸点金属化的后钝化层。 延伸超过下凸块金属化的后钝化层屏蔽下层不受材料的热膨胀系数的不匹配产生的应力。

公开(公告)号：US11804445B2

公开(公告)日：2023-10-31

申请号：US17244754

申请日：2021-04-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Heh-Chang Huang ,  Fu-Jen Li ,  Pei-Haw Tsao ,  Shyue-Ter Leu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214

Abstract: A chip package structure is provided. The chip package structure includes a first chip structure including a substrate and an interconnect layer over the substrate. The chip package structure includes a second chip structure over the interconnect layer. The chip package structure includes a first conductive bump connected between the interconnect layer and the second chip structure. The chip package structure includes a conductive pillar over the interconnect layer. The chip package structure includes a molding layer over the interconnect layer and surrounding the second chip structure, the first conductive bump, and the conductive pillar. The chip package structure includes a second conductive bump over a first surface of the conductive pillar. The first surface faces away from the first chip structure.

公开(公告)号：US10008480B2

公开(公告)日：2018-06-26

申请号：US15722758

申请日：2017-10-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Chih Yew ,  Fu-Jen Li ,  Po-Yao Lin ,  Kuo-Chuan Liu

IPC: H05K1/11 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H05K1/0271 ,  H05K1/11 ,  H05K2201/09063 ,  H05K2201/10378 ,  H05K2201/10613 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors.