公开(公告)号：US20170110408A1

公开(公告)日：2017-04-20

申请号：US14887047

申请日：2015-10-19

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/538 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L21/768

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/0579 ,  H01L2224/05839 ,  H01L2224/08245 ,  H01L2224/29009 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73251 ,  H01L2224/73265 ,  H01L2224/9222 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/35121 ,  H01L2924/3862 ,  H01L2924/00014 ,  H01L2224/291 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00 ,  H01L2924/0781 ,  H01L2924/0665 ,  H01L2224/08 ,  H01L2224/80 ,  H01L2224/48

Abstract: An integrated circuit (IC) die including a top surface and a bottom surface, a plurality of spaced apart ground connection traces positioned between the top surface and the bottom surface; with a hole in the die exposing the plurality of spaced apart ground connection traces.

公开(公告)号：US20160181122A1

公开(公告)日：2016-06-23

申请号：US14581233

申请日：2014-12-23

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Shu Hui Ooi ,  Anis Fauzi Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L21/48 ,  C25D17/08 ,  C25D7/00 ,  H01L23/495 ,  C25D5/02

CPC classification number: H01L21/4821 ,  C25D5/022 ,  C25D7/00 ,  C25D17/08 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/0002 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of making Flat No-Lead Packages with plated lead surfaces exposed on lateral faces thereof. The method includes providing a plurality of Flat No-Lead Packages having severed, unplated lead surfaces exposed on lateral faces thereof and having plated lead surfaces exposed on bottom faces thereof. The method further includes batch electroplating the severed unplated lead surfaces of the plurality of Flat No-Lead Packages.

Abstract translation: 一种制造平面无铅封装的方法，其电镀引线表面暴露在其侧面上。 该方法包括提供多个平面无铅封装，其具有暴露在其侧面上的切断的未镀层的引线表面，并且具有暴露在其底面上的电镀引线表面。 该方法还包括批量电镀多个扁平无铅封装的切断的未镀层的引线表面。

公开(公告)号：US20150228581A1

公开(公告)日：2015-08-13

申请号：US14691660

申请日：2015-04-21

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Sueann Lim Wei Fen ,  Sarel Bin Ismail

IPC: H01L23/532 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L23/544

CPC classification number: H01L23/49541 ,  H01L21/4821 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/5328 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27312 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/83862 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method of making an integrated circuit (“IC”) device includes forming a lead frame in a lead frame strip. Only portions of the lead frame are plated with a conductor. A die pad is attached to an unplated portion of said lead frame.

Abstract translation: 一种制造集成电路（“IC”）器件的方法包括在引线框条中形成引线框架。 只有引线框架的一部分镀有导体。 芯片焊盘连接到所述引线框架的未镀层部分。

公开(公告)号：US09859197B2

公开(公告)日：2018-01-02

申请号：US14691660

申请日：2015-04-21

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Sueann Lim Wei Fen ,  Sarel Bin Ismail

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/00 ,  H01L23/532 ,  H01L23/544 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49541 ,  H01L21/4821 ,  H01L21/4842 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/5328 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/27312 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/83862 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A method of making an integrated circuit (“IC”) device includes forming a lead frame in a lead frame strip. Only portions of the lead frame are plated with a conductor. A die pad is attached to an unplated portion of said lead frame.

公开(公告)号：US09496206B2

公开(公告)日：2016-11-15

申请号：US14683277

申请日：2015-04-10

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L21/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49551 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49586 ,  H01L23/49589 ,  H01L51/56 ,  H01L2224/97

Abstract: A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second sub-leadframe connected by tiebars (111, 121) to a frame (130); and each link having a neck (151) suitable for bending the link, the necks arrayed in a line (170) operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

Abstract translation: 一种用于电子系统的引线框架（100），包括通过链接（150）连接到第二子引线框架（120）的第一子引线框架（110），所述第一和第二子引线框架通过连杆（111,121）连接到 框架（130）; 并且每个连杆具有适于弯曲所述连杆的颈部（151），所述颈部排列成可操作为用于使所述颈部可操作为旋转枢轴的所述第二子引线框架朝向所述第一子引线框架弯曲的轴线的线（170）。

公开(公告)号：US09324640B1

公开(公告)日：2016-04-26

申请号：US14532743

申请日：2014-11-04

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng @ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/34 ,  H01L24/37 ,  H01L24/38 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L25/071 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.

Abstract translation: 一种用于形成堆叠半导体封装的方法，包括提供包括至少包括多个端子的LFs的底部引线框（LF）面板。 低边（LS）晶体管连接到第一裸片附着区域。 第一个夹板包括第一个夹紧器和互连件，放置在底部LF面板上。 电介质插入件通过LS晶体管附着在第一夹子上。 高侧（HS）晶体管附着在插入件上。 包括多个第二夹子的第二夹子面板配合以与HS晶体管互连，包括将第二夹板，第一夹板和底部LF面板配合在一起。 LF可以包括第二管芯附着区域和附接在第二管芯附着区域上的控制器管芯，然后控制器的焊盘引线键合到多个端子。

公开(公告)号：US20150214136A1

公开(公告)日：2015-07-30

申请号：US14168720

申请日：2014-01-30

Applicant: Texas Instruments Incorporated

Inventor： Han Meng @Eugene Lee Lee ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/28

CPC classification number: H01L23/49503 ,  H01L21/4842 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/20754 ,  H01L2924/00012

Abstract: A leadframe (300) for use in semiconductor devices, comprising an assembly pad (3010 having rectangular sides, the pad extending, on one pad side (301b), into a lead (302) and, on the opposite pad side (301a), into straps (350) oriented normal to the side (301a) and anchored in adjacent tie bars (313), strap surfaces having recesses (501, 502) suitable for interlocking with packaging materials. The leadframe further includes a plurality of leads (303) parallel to and alternating with the straps.

Abstract translation: 一种用于半导体器件的引线框架（300），包括：组装垫（3010，其具有矩形侧面，所述焊盘在一个焊盘侧（301b）上延伸到引线中），并且在相对的焊盘侧（301a）上， 定位成垂直于侧面（301a）并锚定在相邻的连接杆（313）中的带子（350），具有适于与包装材料互锁的凹部（501,502）的带表面，引线框架还包括多个引线（303） 与皮带平行并交替。

公开(公告)号：US09741643B2

公开(公告)日：2017-08-22

申请号：US15004208

申请日：2016-01-22

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/49565 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

公开(公告)号：US20170213784A1

公开(公告)日：2017-07-27

申请号：US15004208

申请日：2016-01-22

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@Eugene Lee ,  Anis Fauzi bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L23/49565 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49551 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad and first and second dam bars located adjacent to opposite first and second sides of the die attach pad, respectively. A plurality of continuous lead structures extend, uninterrupted by other structure, between opposing ones of the dam bars of horizontally adjacent leadframes. The plurality of integrally connected leadframes are arranged in a plurality of vertical columns, wherein die attach pads in one vertical column are vertically offset from die attach pads in adjacent vertical columns.

公开(公告)号：US20160300784A1

公开(公告)日：2016-10-13

申请号：US14683277

申请日：2015-04-10

Applicant: Texas Instruments Incorporated

Inventor： Lee Han Meng@ Eugene Lee ,  Anis Fauzi Bin Abdul Aziz ,  Sueann Lim Wei Fen

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49551 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49586 ,  H01L23/49589 ,  H01L51/56 ,  H01L2224/97

Abstract: A leadframe (100) for electronic systems comprising a first sub-leadframe (110) connected by links (150) to a second sub-leadframe (120), the first and second sub-leadframe connected by tiebars (111, 121) to a frame (130); and each link having a neck (151) suitable for bending the link, the necks arrayed in a line (170) operable as the axis for bending the second sub-leadframe towards the first sub-leadframe with the necks operable as rotation pivots.

Abstract translation: 一种用于电子系统的引线框架（100），包括通过链接（150）连接到第二子引线框架（120）的第一子引线框架（110），所述第一和第二子引线框架通过连杆（111,121）连接到 框架（130）; 并且每个连杆具有适于弯曲所述连杆的颈部（151），所述颈部排列成可操作为用于使所述颈部可操作为旋转枢轴的所述第二子引线框架朝向所述第一子引线框架弯曲的轴线的线（170）。