公开(公告)号：US20190027700A1

公开(公告)日：2019-01-24

申请号：US16066858

申请日：2017-01-19

Applicant: TORAY INDUSTRIES, INC.

Inventor： Hiroji SHIMIZU ,  Seiichiro MURASE ,  Daisuke SAKAII

IPC: H01L51/05 ,  H01L27/28 ,  H01L51/00

Abstract: An excellent complementary semiconductor device is provided using a simple process. An n-type drive semiconductor device including a substrate; and a source electrode, a drain electrode, a gate electrode, a gate insulating layer, and a semiconductor layer on the substrate; and including a second insulating layer on the opposite side of the semiconductor layer from the gate insulating layer; in which the second insulating layer contains an organic compound containing a bond between a carbon atom and a nitrogen atom; and in which the semiconductor layer contains a carbon nanotube composite having a conjugated polymer attached to at least a part of the surface thereof.

公开(公告)号：US20200244182A1

公开(公告)日：2020-07-30

申请号：US16652579

申请日：2018-10-25

Applicant: TORAY INDUSTRIES, INC.

Inventor： Hiroji SHIMIZU ,  Seiichiro MURASE

IPC: H02M7/48 ,  G06K19/02 ,  G06K19/07 ,  H01L27/088 ,  H01L27/10 ,  H01L29/786 ,  C01B32/158

Abstract: An object of the present invention is to provide an excellent integrated circuit by a simple process. The present invention is an integrated circuit, which includes at least a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory and in which the memory array includes a first semiconductor element having a first semiconductor layer, the rectifying circuit includes a second semiconductor element having a second semiconductor layer, the logic circuit includes a third semiconductor element having a third semiconductor layer, the first semiconductor element is a memory element, the second semiconductor element is a rectifying element, the third semiconductor element is a logic element, the second semiconductor layer is a functional layer exhibiting a rectifying action, the third semiconductor layer is a channel layer of a logic element, and all of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer and all of the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.

公开(公告)号：US20210057822A1

公开(公告)日：2021-02-25

申请号：US16978490

申请日：2019-03-04

Applicant: TORAY INDUSTRIES, INC.

Inventor： Yoshihiro KARIYA ,  Kenta NOGUCHI ,  Hiroji SHIMIZU ,  Seiichiro MURASE ,  Hisashi NISHIKAWA

IPC: H01Q7/00 ,  H04B1/59 ,  H04B5/00 ,  H01Q1/22 ,  H04B5/02

Abstract: A wireless communication device includes: an antenna for transmitting and receiving a radio wave, a rectifying circuit that is connected to the antenna and rectifies the radio wave received by the antenna to generate voltage, an internal circuit that operates by the voltage generated by the rectifying circuit, and a switch circuit that is disposed contactlessly with respect to the antenna and operates on the basis of an output signal of the internal circuit, wherein the switch circuit includes a coupling wiring and a switch element, and the operation of the switch element varies the impedance of the antenna so that communication can be carried out.

公开(公告)号：US20180277619A1

公开(公告)日：2018-09-27

申请号：US15764197

申请日：2016-10-14

Applicant: TORAY INDUSTRIES, INC.

Inventor： Hiroji SHIMIZU ,  Junji WAKITA ,  Seiichiro MURASE

IPC: H01L49/02 ,  H01L27/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L21/027 ,  H01L21/288 ,  G06K19/077

CPC classification number: H01L28/40 ,  G06K19/0775 ,  H01G4/008 ,  H01G4/18 ,  H01G4/206 ,  H01G4/33 ,  H01G4/40 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02145 ,  H01L21/02153 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/0274 ,  H01L21/288 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203

Abstract: Provided is a capacitor that has good bonding between the dielectric layer and the conductive layer, has a characteristic of low ESR, and keeps leak current suppressed. The capacitor contains a dielectric layer and a conductive film and is characterized in that the dielectric layer contains an organic compound and a metal compound and that the conductive film contains a conductive material and an organic compound.

公开(公告)号：US20180224392A1

公开(公告)日：2018-08-09

申请号：US15748819

申请日：2016-08-08

Applicant: TORAY INDUSTRIES, INC.

Inventor： Kazuki ISOGAI ,  Seiichiro MURASE ,  Hiroji SHIMIZU

IPC: G01N27/414 ,  H01L51/05 ,  H01L51/00

CPC classification number: G01N27/4145 ,  B82Y15/00 ,  B82Y30/00 ,  G01N27/126 ,  G01N27/3275 ,  G01N27/3278 ,  G01N27/414 ,  G01N27/4146 ,  H01L29/786 ,  H01L51/0003 ,  H01L51/0036 ,  H01L51/004 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0094 ,  H01L51/05 ,  H01L51/0545

Abstract: The present invention is to provide a semiconductor element achieving a high-level detection sensitivity when utilized as a sensor. The present invention relates to a semiconductor element including an organic film, a first electrode, a second electrode, and a semiconductor layer, in which the first electrode, the second electrode and the semiconductor layer are formed on the organic film, the semiconductor layer is arranged between the first electrode and the second electrode, the semiconductor layer contains a carbon nanotube, and the organic film has a water contact angle of 5° or more and 50° or less.

公开(公告)号：US20200321399A1

公开(公告)日：2020-10-08

申请号：US16303873

申请日：2017-05-29

Applicant: TORAY INDUSTRIES, INC.

Inventor： Shota KAWAI ,  Seiichiro MURASE ,  Hiroji SHIMIZU

IPC: H01L27/28 ,  G06K19/077 ,  H01L51/00 ,  H01L51/10

Abstract: A memory array includes: a plurality of first wires; at least one second wire crossing the first wires; and a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the memory elements being formed on a substrate.

公开(公告)号：US20180327530A1

公开(公告)日：2018-11-15

申请号：US15774936

申请日：2016-11-21

Applicant: TORAY INDUSTRIES, INC.

Inventor： Junji WAKITA ,  Hiroji SHIMIZU ,  Shota KAWAI ,  Seiichiro MURASE

IPC: C08F220/14 ,  H01L51/00 ,  C08F220/32 ,  C08G18/71 ,  C08G18/34 ,  C08F212/08 ,  G03F7/16 ,  G03F7/20 ,  G03F7/32 ,  G03F7/40 ,  H01L27/28 ,  H01L51/05 ,  G06K19/077

CPC classification number: C08F220/14 ,  C08F212/08 ,  C08F220/32 ,  C08F2220/1841 ,  C08F2220/325 ,  C08F2800/20 ,  C08G18/34 ,  C08G18/71 ,  G03F7/004 ,  G03F7/038 ,  G03F7/162 ,  G03F7/168 ,  G03F7/2004 ,  G03F7/322 ,  G03F7/40 ,  G06K19/07773 ,  H01B1/22 ,  H01B5/16 ,  H01L21/288 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/1159 ,  H01L27/28 ,  H01L27/283 ,  H01L29/786 ,  H01L51/004 ,  H01L51/0043 ,  H01L51/0048 ,  H01L51/05 ,  H01L51/0558

Abstract: An object of the present invention is to provide a ferroelectric memory element which has a low driving voltage and which can be formed by coating. The present invention provides a ferroelectric memory element including at least: a first conductive film; a second conductive film; and a ferroelectric layer provided between the first conductive film and the second conductive film; wherein the ferroelectric layer contains ferroelectric particles and an organic component, and wherein the ferroelectric particles have an average particle size of from 30 to 500 nm.

公开(公告)号：US20180210337A1

公开(公告)日：2018-07-26

申请号：US15743199

申请日：2016-08-10

Applicant: TORAY INDUSTRIES, INC.

Inventor： Junji WAKITA ,  Hiroji SHIMIZU ,  Seiichiro MURASE

IPC: G03F7/031 ,  G03F7/095 ,  G03F7/09 ,  G03F7/20 ,  G03F7/004 ,  G03F7/16 ,  G03F7/32 ,  H01L23/66 ,  H01L21/48 ,  G06K19/077 ,  H01Q1/38

CPC classification number: G03F7/031 ,  B82Y30/00 ,  B82Y40/00 ,  G03F7/0035 ,  G03F7/0045 ,  G03F7/0047 ,  G03F7/027 ,  G03F7/0388 ,  G03F7/094 ,  G03F7/095 ,  G03F7/16 ,  G03F7/168 ,  G03F7/2002 ,  G03F7/2022 ,  G03F7/322 ,  G06K19/077 ,  G06K19/07722 ,  H01L21/4853 ,  H01L21/4867 ,  H01L23/66 ,  H01L29/786 ,  H01L51/0036 ,  H01L51/0043 ,  H01L51/0048 ,  H01L51/05 ,  H01L2223/6677 ,  H01P11/00 ,  H01Q1/2208 ,  H01Q1/38 ,  H01Q7/00 ,  H05K1/09 ,  H05K1/16 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/954

Abstract: An object of the present invention is to provide a method for accurately forming an antenna substrate as well as an antenna substrate with wiring line and electrode by a coating method. One aspect of the present invention provides a method for producing an antenna substrate with wiring line and electrode including the steps of: (1) forming a coating film using a photosensitive paste containing a conductive material and a photosensitive organic component on an insulating substrate; (2-A) processing the coating film into a pattern corresponding to an antenna by photolithography; (2-B) processing the coating film into a pattern corresponding to a wiring line; (2-C) processing the coating film into a pattern corresponding to an electrode; (3-A) curing the pattern corresponding to an antenna into an antenna; (3-B) curing the pattern corresponding to a wiring line into a wiring line; and (3-C) curing the pattern corresponding to an electrode into an electrode.