利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.029 秒)

    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20100051906A1

    公开(公告)日：2010-03-04

    申请号：US12549140

    申请日：2009-08-27

    申请人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Hiroto Honda ,  Kei Masunishi ,  Shinji Murai ,  Masumi Saitoh

    发明人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Hiroto Honda ,  Kei Masunishi ,  Shinji Murai ,  Masumi Saitoh

    IPC分类号： H01L31/0352

    CPC分类号： H01L27/14645 ,  H01L27/14683 ,  H01L31/0352

    摘要： A semiconductor device for correcting an input signal and outputting a corrected signal are provided. The semiconductor device includes a semiconductor layer, a plurality of first conductors formed on one of faces of the semiconductor layer and serving as input terminals to which a signal is input, second conductors of the number larger than that of the first conductors at density higher than that of the first conductors, formed on the other face of the semiconductor layer, a high impurity concentration region provided on the semiconductor layer side of an interface between the second conductor and the semiconductor layer, an insulating layer formed on the other face, and a plurality of third conductors formed on the insulating layer and serving as output terminals for outputting the processed signal.

    摘要翻译： 提供了用于校正输入信号并输出​​校正信号的半导体器件。 半导体器件包括半导体层，形成在半导体层的一个表面上并用作输入信号的输入端的多个第一导体，第二导​​体的数量大于第一导体的密度高于 在半导体层的另一面形成的第一导体的第一导体的高杂质浓度区域设置在第二导体和半导体层之间的界面的半导体层侧，形成在另一面上的绝缘层， 多个第三导体，形成在绝缘层上并用作用于输出处理信号的输出端。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08053758B2

    公开(公告)日：2011-11-08

    申请号：US12549140

    申请日：2009-08-27

    申请人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Hiroto Honda ,  Kei Masunishi ,  Shinji Murai ,  Masumi Saitoh

    发明人： Takashi Yamauchi ,  Yoshifumi Nishi ,  Hiroto Honda ,  Kei Masunishi ,  Shinji Murai ,  Masumi Saitoh

    IPC分类号： H01L29/08 ,  H01L29/15 ,  H01L31/0352 ,  H01L31/0256 ,  H01L31/0232

    CPC分类号： H01L27/14645 ,  H01L27/14683 ,  H01L31/0352

    摘要： A semiconductor device for correcting an input signal and outputting a corrected signal are provided. The semiconductor device includes a semiconductor layer, a plurality of first conductors formed on one of faces of the semiconductor layer and serving as input terminals to which a signal is input, second conductors of the number larger than that of the first conductors at density higher than that of the first conductors, formed on the other face of the semiconductor layer, a high impurity concentration region provided on the semiconductor layer side of an interface between the second conductor and the semiconductor layer, an insulating layer formed on the other face, and a plurality of third conductors formed on the insulating layer and serving as output terminals for outputting the processed signal.

    摘要翻译： 提供了用于校正输入信号并输出​​校正信号的半导体器件。 半导体器件包括半导体层，形成在半导体层的一个表面上并用作输入信号的输入端的多个第一导体，第二导​​体的数量大于第一导体的密度高于 在半导体层的另一面形成的第一导体的第一导体的高杂质浓度区域设置在第二导体和半导体层之间的界面的半导体层侧，形成在另一面上的绝缘层， 多个第三导体，形成在绝缘层上并用作用于输出处理信号的输出端。

    Semiconductor device and manufacturing method of same
    3.
    发明授权
    Semiconductor device and manufacturing method of same 有权
    半导体器件及其制造方法

    公开(公告)号：US08399926B2

    公开(公告)日：2013-03-19

    申请号：US13283264

    申请日：2011-10-27

    申请人： Masumi Saitoh ,  Ken Uchida

    发明人： Masumi Saitoh ,  Ken Uchida

    IPC分类号： H01L27/12

    CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

    摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 失效
    半导体存储器件

    公开(公告)号：US20120075928A1

    公开(公告)日：2012-03-29

    申请号：US13246996

    申请日：2011-09-28

    申请人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    发明人： Jun Fujiki ,  Kiwamu Sakuma ,  Naoki Yasuda ,  Yukio Nakabayashi ,  Masumi Saitoh

    IPC分类号： H01L29/792 ,  G11C11/34 ,  G11C11/412

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/11568 ,  H01L29/4234

    摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.

    摘要翻译： 在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息 到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置 要写

    Semiconductor device and manufacturing method of same
    6.
    发明授权
    Semiconductor device and manufacturing method of same 有权
    半导体器件及其制造方法

    公开(公告)号：US08076231B2

    公开(公告)日：2011-12-13

    申请号：US12401704

    申请日：2009-03-11

    申请人： Masumi Saitoh ,  Ken Uchida

    发明人： Masumi Saitoh ,  Ken Uchida

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

    摘要： A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

    摘要翻译： 提供了根据侧面取向和载流子极性优化的应变方向的FinFET和纳米线晶体管，以及用于实现其的SMT引入制造方法。 半导体器件包括具有半导体衬底的pMISFET，形成在衬底上部的矩形固体半导体层，具有平行于衬底的主平面的顶表面和垂直于衬底的（100）面的侧面 基板的主平面，形成在矩形半导体层中的沟道区，至少形成在矩形层的侧面上的栅极绝缘膜，栅极绝缘膜上的栅电极和形成在矩形半导体层中的源/漏区， 在其间插入通道区域。 通道区域在与基板主平面垂直的方向上施加压缩应变。 还公开了该装置的制造方法。

    Nanowire channel field effect device and method for manufacturing the same
    7.
    发明授权
    Nanowire channel field effect device and method for manufacturing the same 有权
    纳米线通道场效应装置及其制造方法

    公开(公告)号：US08999801B2

    公开(公告)日：2015-04-07

    申请号：US13236199

    申请日：2011-09-19

    申请人： Kensuke Ota ,  Masumi Saitoh ,  Toshinori Numata

    发明人： Kensuke Ota ,  Masumi Saitoh ,  Toshinori Numata

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

    CPC分类号： H01L29/0673 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/78696

    摘要： A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions.

    摘要翻译： 根据实施例的半导体器件包括：形成在绝缘膜上的多晶半导体层，所述多晶半导体层包括第一区域和第二和第三区域，所述第二区域和第三区域各自具有比所述第一区域更大的宽度，所述第二和第三区域中的一个是 连接到第一区域; 形成在所述多晶半导体层的所述第一区域的至少一侧面上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及由绝缘材料制成的栅极侧壁，所述栅极侧壁形成在所述第二和第三区域侧面上的所述栅电极的侧面上。 第一区域中每单位体积杂质的含量大于第二和第三区域中每单位体积杂质的含量。

    Semiconductor device and method of manufacturing the same
    9.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08518769B2

    公开(公告)日：2013-08-27

    申请号：US13415592

    申请日：2012-03-08

    申请人： Kensuke Ota ,  Toshinori Numata ,  Masumi Saitoh ,  Chika Tanaka

    发明人： Kensuke Ota ,  Toshinori Numata ,  Masumi Saitoh ,  Chika Tanaka

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/786 ,  H01L29/00 ,  H01L29/785 ,  H01L29/78696

    摘要： A semiconductor device of an embodiment includes: an insulating film including: a first region extending in a first direction; second and third regions arranged at a distance from each other; and fourth and fifth regions each having a concave shape, the fourth and fifth regions each having a smaller film thickness than a film thickness of each of the first through third regions; a semiconductor layer formed in a direction from the fourth region toward the fifth region, the semiconductor layer having a smaller width than a width of each of source and drain regions, the semiconductor layer being connected to the source and drain regions; a gate electrode placed on the opposite side of a gate insulating film from the semiconductor layer on the first region; and a gate sidewall formed on a side face of the gate electrode.

    摘要翻译： 实施例的半导体器件包括：绝缘膜，包括：沿第一方向延伸的第一区域; 第二和第三区域彼此相隔一定距离; 第四和第五区域各自具有凹形形状，第四和第五区域各自具有比每个第一至第三区域的膜厚度更薄的膜厚度; 在从第四区域朝向第五区域的方向上形成的半导体层，所述半导体层的宽度小于源极和漏极区域的宽度，所述半导体层连接到所述源极和漏极区域; 栅极电极，位于栅极绝缘膜的与第一区域上的半导体层相反的一侧; 以及形成在栅电极的侧面上的栅极侧壁。

    Semiconductor device manufacturing method
    10.
    发明授权
    Semiconductor device manufacturing method 有权
    半导体器件制造方法

    公开(公告)号：US08492219B2

    公开(公告)日：2013-07-23

    申请号：US13487295

    申请日：2012-06-04

    申请人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    发明人： Masumi Saitoh ,  Toshinori Numata ,  Yukio Nakabayashi

    IPC分类号： H01L21/8234 ,  H01L21/337 ,  H01L21/8232 ,  H01L21/336 ,  H01L21/00

    CPC分类号： H01L27/0207 ,  H01L21/266 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66628 ,  H01L29/785

    摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

    摘要翻译： 在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极 形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案， 执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源 在栅电极的两侧形成有引线区域。