公开(公告)号：US4314226A

公开(公告)日：1982-02-02

申请号：US109489

申请日：1980-01-04

申请人： Takeshi Oguro ,  Teruyoshi Mihara ,  Tamotsu Tominaga ,  Masami Takeuchi

发明人： Takeshi Oguro ,  Teruyoshi Mihara ,  Tamotsu Tominaga ,  Masami Takeuchi

IPC分类号： G01L9/04 ,  G01L9/00 ,  H01L29/84 ,  G01L1/22

CPC分类号： G01L19/147 ,  H01L29/84

摘要： A pressure sensor having a silicon diaphragm whose opposite surfaces are subjected to fluid pressures for measurement. The diaphragm includes a diffused resistor as a pressure-sensitive element on a silicon base, a protective layer composed of a silicon epitaxial layer opposite in conductive type to the resistor and formed on the diffused resistor in order to prevent the resistor from being exposed to a corresponding fluid pressure, and an electrically insulating layer formed on an outer surface of the protective layer.

摘要翻译： 一种具有硅膜片的压力传感器，其相对表面经受用于测量的流体压力。 隔膜包括作为硅基底上的压敏元件的扩散电阻器，由与电阻器相反的导电类型的硅外延层构成的保护层，并形成在扩散电阻器上，以防止电阻器暴露于 相应的流体压力，以及形成在保护层的外表面上的电绝缘层。

公开(公告)号：US4287501A

公开(公告)日：1981-09-01

申请号：US109484

申请日：1980-01-04

申请人： Tamotsu Tominaga ,  Teruyoshi Mihara ,  Takeshi Oguro ,  Masami Takeuchi

发明人： Tamotsu Tominaga ,  Teruyoshi Mihara ,  Takeshi Oguro ,  Masami Takeuchi

IPC分类号： G01L13/06 ,  G01L9/00 ,  G01L15/00 ,  H01L29/84

CPC分类号： G01L19/142 ,  G01L19/0038 ,  G01L19/0084

摘要： A pair of semiconductor diaphragm blocks, each having a diaphragm on a front surface of which a diffused resistor is formed as a pressure-sensitive element, and a circumferential support integral therewith, are confined within a sealed hollow package and bonded at their circumferential supports to opposite inside surfaces of the package such that the front surfaces of the diaphragms are positioned within a vacuum space within the package. This package is provided with through holes through which fluid pressures subject to measurement are introduced so as to arrive at the back surfaces of the diaphragms.

摘要翻译： 一对半导体膜片块，其前表面上形成有扩散电阻器作为压敏元件的隔膜和与其形成一体的周向支撑件，被限制在密封的中空包装内并且在其周向支撑件处粘合 使得膜片的前表面位于包装内的真空空间内。 该包装件设置有通孔，通过该通孔引入测量的流体压力以到达隔膜的后表面。

公开(公告)号：US4276533A

公开(公告)日：1981-06-30

申请号：US116795

申请日：1980-01-30

申请人： Tamotsu Tominaga ,  Teruyoshi Mihara ,  Takeshi Oguro ,  Masami Takeuchi

发明人： Tamotsu Tominaga ,  Teruyoshi Mihara ,  Takeshi Oguro ,  Masami Takeuchi

IPC分类号： G01L9/04 ,  G01L9/00 ,  G01L1/22

CPC分类号： G01L19/146 ,  G01L19/0038 ,  G01L19/0084 ,  G01L19/147 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2924/16152

摘要： A diaphragm assembly includes a silicon diaphragm block which has a diaphragm at an eccentric position thereof, a diffused resistor formed as a pressure-sensitive element on a front surface of the diaphragm, and a silicon support plate bonded to the diaphragm block so as to cover a back surface of the diaphragm. The diaphragm assembly is accommodated sealingly within and bonded to the inside of a hollow package at an end portion of the assembly remote from the diaphragm in the direction of extension of the bonded surfaces of the block and the support plate. The front surface of the diaphragm and the diffused resistor thereon are exposed to a vacuum while a fluid pressure subject to measurement is introduced through a passage extending through the package and the end portion of the assembly bonded to the package so as to arrive at a back surface of the diaphragm.

摘要翻译： 膜片组件包括在其偏心位置处具有隔膜的硅隔膜块，在隔膜的前表面上形成为压敏元件的扩散电阻器，以及结合到隔膜块的硅支撑板，以覆盖 隔膜的后表面。 隔膜组件在远离隔膜的组件的端部沿块体和支撑板的接合表面的延伸方向密封地容纳在中空包装体的内部并结合到中空包装体的内部。 膜片的前表面和其上的扩散电阻器暴露于真空，同时通过延伸穿过封装件的通道和接合到封装件的组件的端部部分引入测量的流体压力，以便到达后面 隔膜表面。

公开(公告)号：US4315236A

公开(公告)日：1982-02-09

申请号：US109476

申请日：1980-01-04

申请人： Tamotsu Tominaga ,  Teruyoshi Mihara ,  Takeshi Oguro ,  Masami Takeuchi

发明人： Tamotsu Tominaga ,  Teruyoshi Mihara ,  Takeshi Oguro ,  Masami Takeuchi

IPC分类号： G01L9/04 ,  G01L9/00 ,  H01L29/84 ,  G01L1/22

CPC分类号： G01L19/0084 ,  G01L19/146 ,  G01L19/147 ,  G01L9/0054

摘要： A sensor block is disposed within a package and includes a semiconductor diaphragm and a circumferential support bonded to the inside of the package. The semiconductor diaphragm is provided with at least one diffused resistor layer formed thereon as a pressure-sensitive element, one surface of the diaphragm being subjected to a reference pressure whereas the other surface is subjected to a fluid pressure to be measured. A diaphragm breakage detecting element including an electrical conductor filament is provided zigzagging back and forth laterally across the boundary between the diaphragm and the circumferential support, the point subject to maximum stress, the conductor filament material being of substantially the same mechanical strength as the diaphragm material, so that, when the diaphragm is broken, the conductor filament is also broken, thus allowing immediate indication of the diaphragm breakage. The detecting element may include a U-shaped protrusion extending radially inwards, substantially reaching the center of the diaphragm in order to detect breakage of the diaphragm at the center thereof, where a second maximum stress occurs.

摘要翻译： 传感器块设置在封装内，并且包括半导体隔膜和结合到封装内部的周向支撑件。 半导体膜片设置有形成在其上的至少一个扩散电阻层作为压敏元件，隔膜的一个表面受到基准压力，而另一个表面经受要测量的流体压力。 包括电导体细丝的隔膜破损检测元件横向跨越隔膜和周向支撑件之间的边界并且受到最大应力的点的横向前后方向设置，导体细丝材料具有与隔膜材料基本相同的机械强度 ，因此当隔膜破裂时，导体细丝也会断裂，从而立即显示隔膜破损。 检测元件可以包括径向向内延伸的U形突起，基本上到达隔膜的中心，以便检测在其中心处出现第二最大应力的隔膜的断裂。

公开(公告)号：US4314225A

公开(公告)日：1982-02-02

申请号：US55755

申请日：1979-07-09

申请人： Tamotsu Tominaga ,  Teruyoshi Mihara

发明人： Tamotsu Tominaga ,  Teruyoshi Mihara

IPC分类号： G01L9/04 ,  G01L9/00 ,  H01L23/057 ,  H01L23/498 ,  H01L29/84 ,  G01L1/22

CPC分类号： G01L19/0084 ,  G01L19/146 ,  G01L19/147 ,  H01L23/057 ,  H01L23/49805 ,  H01L29/84 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10158 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/16195

摘要： A pressure sensor of the type having a semiconductor diaphragm such as a silicon diaphragm which is formed with at least one diffused resistor in a surface region on one side thereof. A silicon block having the diaphragm is bonded to the inside of a box-like package such that the diffused resistor is exposed in a vacuum chamber defined in the package and that a fluid pressure can arrive at the back side of the diaphragm through a hole of the package. To minimize unwanted straining of the silicon diaphragm by thermal influences, the package is made of a material such as mullite whose linear expansion coefficient is close to that of silicon. To prevent an accidental change in the output characteristic of the sensor by the influence of an unintended external force, the package is supported above a base plate by pillar-like lead frames and confined in a space provided by fixing a cap to the base plate. A pressure introduction pipe is attached to either the base plate or the cap.

摘要翻译： 这种类型的压力传感器具有诸如硅膜片的半导体膜片，该膜片在其一侧的表面区域中形成有至少一个扩散电阻器。 具有隔膜的硅块结合到箱状封装的内部，使得扩散电阻器暴露在限定在封装中的真空室中，并且流体压力可以通过孔的一个孔到达隔膜的后侧 包装。 为了通过热影响最小化硅膜的不希望的应变，封装由诸如莫来石的材料制成，其线膨胀系数接近硅的膨胀系数。 为了防止由于非预期的外力的影响，传感器的输出特性的意外变化，封装通过柱状引线框架支撑在基板上方，并限制在通过将盖固定到基板上而提供的空间中。 压力引入管连接到基板或盖上。

公开(公告)号：US5635742A

公开(公告)日：1997-06-03

申请号：US660211

申请日：1996-06-03

申请人： Masakatsu Hoshi ,  Teruyoshi Mihara

发明人： Masakatsu Hoshi ,  Teruyoshi Mihara

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L27/10

CPC分类号： H01L29/0696 ,  H01L29/41741 ,  H01L29/7809 ,  H01L29/41766 ,  H01L29/456

摘要： A lateral double-diffused MOSFET has a semiconductor substrate, a drain region formed on the substrate, a gate insulation film formed on the drain region, a gate electrode formed on the gate insulation film, source and drain openings formed through the gate electrode, a first conductive region formed under the drain region, a source electrode formed on the source openings, a drain electrode formed on the drain openings, and second conductive regions for connecting the drain electrode to the first conductive region. The source and drain openings are cyclically arranged so that at least two rows of source openings are arranged between adjacent drain openings, to reduce the ON resistance of the MOSFET.

摘要翻译： 横向双扩散MOSFET具有半导体基板，形成在基板上的漏极区域，形成在漏极区域上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，通过栅电极形成的源极和漏极开口， 形成在漏极区域下方的第一导电区域，形成在源极开口上的源极电极，形成在漏极开口上的漏电极，以及用于将漏电极连接到第一导电区域的第二导电区域。 源极和漏极开口循环布置，使得至少两排源极开口布置在相邻的漏极开口之间，以降低MOSFET的导通电阻。

公开(公告)号：USRE35405E

公开(公告)日：1996-12-17

申请号：US288731

申请日：1994-08-12

申请人： Yoshinori Murakami ,  Teruyoshi Mihara

发明人： Yoshinori Murakami ,  Teruyoshi Mihara

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78 ,  H01L21/338

CPC分类号： H01L29/66416 ,  H01L29/66666 ,  H01L29/7722 ,  H01L29/7827 ,  H01L29/4232 ,  H01L29/4238 ,  Y10S148/05

摘要： A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

摘要翻译： 一种通过在衬底上形成U形绝缘栅来制造半导体器件的方法，蚀刻衬底以露出U形绝缘栅极的侧壁，用掩模材料覆盖暴露部分，仅形成掩模材料的侧壁 邻接于暴露的U形绝缘栅极，垂直蚀刻衬底以形成沟槽，在沟槽上形成半导体区域并将金属埋入槽中。

公开(公告)号：US4931846A

公开(公告)日：1990-06-05

申请号：US185387

申请日：1988-04-25

申请人： Teruyoshi Mihara

发明人： Teruyoshi Mihara

IPC分类号： H01L27/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L27/0727 ,  H01L29/1095 ,  H01L29/0626 ,  H01L29/0878

摘要： A vertical MOSFET device has a first conductivity type substrate layer serving as a drain, a second conductivity type channel region extending into said substrate layer from a top surface, and a first conductivity type source region extending into the channel region from the top surface. The channel region has a peripheral subregion extending deeply into the substrate layer from the top surface under an insulated gate electrode, and a shallow central subregion shallower than the peripheral subregion. There is further provided a second conductivity type underlying layer formed under the shallow central subregion so as to form a voltage regulating diode with the channel region at a position shallower than the bottom of the peripheral subregion.

公开(公告)号：US4893158A

公开(公告)日：1990-01-09

申请号：US209237

申请日：1988-06-20

申请人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

发明人： Teruyoshi Mihara ,  Yukitsugu Hirota ,  Yukio Hiramoto ,  Tsutomu Matsushita

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H03K17/082

CPC分类号： H01L29/7815 ,  H01L27/0251 ,  H01L27/0623 ,  H03K17/0822 ,  H01L2924/0002

摘要： A power MOSFET is provided with a protective circuit including a monitor MOSFET whose drain is connected with the drain of the power MOSFET, a monitor resistor connected betwen the sources of the power and monitor MOSFETs, and a monitor transistor for decreasing a gate voltage of the power MOSFET when a voltage across the monitor resistor exceeds a predetermined level representing a dangerous condition of the device.

摘要翻译： 功率MOSFET具有保护电路，该保护电路包括监控MOSFET，漏极与功率MOSFET的漏极连接，监控电阻连接在电源和监视器MOSFET的源极之间，监视晶体管用于降低栅极电压 当监视器电阻两端的电压超过表示设备的危险状况的预定电平时，功率MOSFET。

公开(公告)号：US4862233A

公开(公告)日：1989-08-29

申请号：US63116

申请日：1987-06-17

申请人： Tsutomu Matsushita ,  Teruyoshi Mihara

发明人： Tsutomu Matsushita ,  Teruyoshi Mihara

IPC分类号： H01L27/08 ,  H01L21/76 ,  H01L27/088 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/7802

摘要： Vertical MOS and another component such as CMOS are made in a single semiconductor substrate having a highly doped underlying layer and a lightly doped epitaxial surface layer of a first conductivity type. The vertical MOS includes a channel region of a second conductivity type, formed in the surface layer, and a source region of the first conductivity type, formed in the channel region. The channel region is made deep and joined with the highly doped underlying layer to form a first Zener diode for regulating a drain-source voltage. A drain electrode is formed on the bottom surface of the substrate and connected to a power supply, and a topside source electrode is connected to a load. The vertical MOS is surrounded, and separated from the CMOS, by a grounded guard ring region of the second conductivity type, formed in the surface layer. The guard ring region is also made deep and joined with the underlying layer.

摘要翻译： 垂直MOS和诸如CMOS的另一部件在具有高掺杂的下层和具有第一导电类型的轻掺杂外延表面层的单个半导体衬底中制成。 垂直MOS包括形成在表面层中的第二导电类型的沟道区域和形成在沟道区域中的第一导电类型的源极区域。 沟道区域被制成深并与高度掺杂的下层连接，以形成用于调节漏极 - 源极电压的第一齐纳二极管。 漏极电极形成在基板的底面上，与电源连接，顶侧的源电极与负载连接。 垂直MOS通过形成在表面层中的第二导电类型的接地保护环区域被包围并与CMOS分离。 保护环区域也是深层的，并与底层相连。