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    Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
    3.
    发明授权
    Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same 有权
    并联串联晶体管串的可编程存储器阵列结构及其制造和操作的方法

    公开(公告)号：US07505321B2

    公开(公告)日：2009-03-17

    申请号：US10335078

    申请日：2002-12-31

    申请人： Roy E. Scheuerlein ,  Christopher Petti ,  Andrew J. Walker ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli ,  Igor Koutnetsov

    发明人： Roy E. Scheuerlein ,  Christopher Petti ,  Andrew J. Walker ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Alper Ilkbahar ,  Luca Fasoli ,  Igor Koutnetsov

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C5/06 ,  G11C8/00

    CPC分类号： H01L27/11568 ,  G11C11/5621 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/1159

    摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

    摘要翻译： 三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F2存储单元布局。 可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。 每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。 块内的一对NAND串共享相同的全局位线。 存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。 存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。 多个层上的NAND串可以连接到单个层上的全局位线。 通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。 不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。 每个存储器级别可以以每级别少于三个掩码来生成。

    Method for fabricating programmable memory array structures incorporating series-connected transistor strings
    4.
    发明授权
    Method for fabricating programmable memory array structures incorporating series-connected transistor strings 有权
    用于制造并入串联晶体管串的可编程存储器阵列结构的方法

    公开(公告)号：US07005350B2

    公开(公告)日：2006-02-28

    申请号：US10335089

    申请日：2002-12-31

    申请人： Andrew J. Walker ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Roy E. Scheuerlein ,  Alper Ilkbahar ,  Luca Fasoli ,  Igor Koutnetsov ,  Christopher Petti

    发明人： Andrew J. Walker ,  En-Hsing Chen ,  Sucheta Nallamothu ,  Roy E. Scheuerlein ,  Alper Ilkbahar ,  Luca Fasoli ,  Igor Koutnetsov ,  Christopher Petti

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11502

    摘要： A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

    摘要翻译： 三维闪存阵列包括具有布置在串联连接的NAND串中的电荷存储电介质的薄膜晶体管，以实现4F 2存储单元布局。 可以仅使用隧穿电流对存储器阵列进行编程和擦除，并且不通过未选择的存储器单元形成泄漏路径。 每个NAND串包括用于分别将NAND串的一端耦合到全局位线的两个块选择器件，另一端连接到共享偏置节点。 块内的一对NAND串共享相同的全局位线。 存储器单元优选地是耗尽型SONOS器件，块选择器件也是如此。 存储器单元可以被编程为接近耗尽阈值电压，并且块选择器件保持在具有接近耗尽模式阈值电压的编程状态。 多个层上的NAND串可以连接到单个层上的全局位线。 通过在每个存储器级别交错NAND串并且每个块使用两个共享偏置节点，对于NAND串的每一端的开关器件需要非常少的附加开销。 不同存储器级别的NAND串优选通过垂直堆叠的通孔连接在一起，每个优选地连接到多于一个的存储器级。 每个存储器级别可以以每级别少于三个掩码来生成。

    Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance
    7.
    发明申请
    Method for using a memory cell comprising switchable semiconductor memory element with trimmable resistance 有权
    一种用于使用具有可调整电阻的可切换半导体存储元件的存储单元的方法

    公开(公告)号：US20070072360A1

    公开(公告)日：2007-03-29

    申请号：US11496986

    申请日：2006-07-31

    申请人： Tanmay Kumar ,  S.B. Herner ,  Roy Scheuerlein ,  Christopher Petti

    发明人： Tanmay Kumar ,  S.B. Herner ,  Roy Scheuerlein ,  Christopher Petti

    IPC分类号： H01L21/8234

    CPC分类号： G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/165 ,  G11C2013/0073 ,  H01L27/101

    摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.

    摘要翻译： 包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲 二极管在正向偏置下，而复位脉冲以二极管反向施加。 通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

    Integrated circuit embodying a non-volatile memory cell
    9.
    发明申请
    Integrated circuit embodying a non-volatile memory cell 审中-公开
    集成电路体现了非易失性存储单元

    公开(公告)号：US20070007577A1

    公开(公告)日：2007-01-11

    申请号：US11175688

    申请日：2005-07-06

    申请人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

    发明人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7883 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 μm from a diffusion region of the capacitor.

    摘要翻译： 提供了包括至少一个存储单元的集成电路。 这样的存储单元又包括晶体管和电容器。 晶体管包括源极，漏极和栅极。 此外，电容器包括阱和栅极。 晶体管的栅极保持与电容器的栅极通信。 在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。 在这样的实施例中，晶体管的阱邻接电容器的阱。 在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

    Rewriteable memory cell comprising a diode and a resistance-switching material
    10.
    发明申请
    Rewriteable memory cell comprising a diode and a resistance-switching material 审中-公开
    包括二极管和电阻切换材料的可重写存储单元

    公开(公告)号：US20060250836A1

    公开(公告)日：2006-11-09

    申请号：US11125939

    申请日：2005-05-09

    申请人： S. Herner ,  Christopher Petti

    发明人： S. Herner ,  Christopher Petti

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

    摘要： In a novel rewriteable nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgOx, CrO2, VO, BN, and AlN. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors.

    摘要翻译： 在形成于基板上方的新型可重写非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NiO，Nb 2 O > 5，TiO 2，HfO 2，Al 2 O 3，MgO， xO，CrO 2，VO，BN和AlN。 在优选实施例中，二极管形成为设置在导体之间的垂直支柱。 可以堆叠多个存储器级别以形成单片三维存储器阵列。 在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。