公开(公告)号：US06976415B2

公开(公告)日：2005-12-20

申请号：US11078063

申请日：2005-03-11

申请人： Tomoe Suzuki ,  Shinji Yuri ,  Kazuhisa Sato ,  Kozo Yamasaki

发明人： Tomoe Suzuki ,  Shinji Yuri ,  Kazuhisa Sato ,  Kozo Yamasaki

IPC分类号： B32B15/08 ,  B32B27/38 ,  H05K1/05 ,  H05K3/00 ,  H05K3/44 ,  B26D3/00

CPC分类号： H05K1/056 ,  B32B15/08 ,  B32B27/38 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0909 ,  H05K2201/09709 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49135 ,  Y10T29/49165 ,  Y10T83/0333 ,  Y10T83/0341 ,  Y10T83/0581 ,  Y10T428/12 ,  Y10T428/12361 ,  Y10T428/15 ,  Y10T428/24298 ,  Y10T428/24314 ,  Y10T428/24917

摘要： The invention provides a method for manufacturing printed wiring substrates which can manufacture printed wiring substrates each having resin dielectric layers of uniform thickness and excellent surface flatness while maintaining favorable cutting performance in a dicing step. A multi-printed wiring-substrate panel is manufactured which includes a metal plate having a first main surface and a second main surface, and resin dielectric layers disposed on the first and second main surfaces. The metal plate has first depression portions and second depression portions. The first depression portions are opened at the first main surface and arranged discontinuously along predetermined cutting lines. The second depression portions are opened at the second main surface and arranged discontinuously along the predetermined cutting lines. The multi-printed wiring-substrate panel is cut along the predetermined cutting lines into a plurality of printed wiring substrates.

摘要翻译： 本发明提供一种制造印刷布线基板的方法，其可以制造印刷布线基板，每个印刷布线基板具有均匀厚度的树脂电介质层和优异的表面平坦度，同时在切割步骤中保持良好的切割性能。 制造了包括具有第一主表面和第二主表面的金属板以及设置在第一和第二主表面上的树脂电介质层的多印刷布线基板。 金属板具有第一凹部和第二凹部。 第一凹陷部分在第一主表面处被打开，并且沿着预定的切割线不连续地布置。 第二凹陷部分在第二主表面处被打开，并且沿着预定切割线不连续地布置。 多个印刷线路基板被沿着预定的切割线切割成多个印刷布线基板。

公开(公告)号：US20050155789A1

公开(公告)日：2005-07-21

申请号：US11078063

申请日：2005-03-11

申请人： Tomoe Suzuki ,  Shinji Yuri ,  Kazuhisa Sato ,  Kozo Yamasaki

发明人： Tomoe Suzuki ,  Shinji Yuri ,  Kazuhisa Sato ,  Kozo Yamasaki

IPC分类号： B32B15/08 ,  B32B27/38 ,  H05K1/05 ,  H05K3/00 ,  H05K3/44 ,  H05K1/03 ,  H05K1/11

CPC分类号： H05K1/056 ,  B32B15/08 ,  B32B27/38 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0909 ,  H05K2201/09709 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49135 ,  Y10T29/49165 ,  Y10T83/0333 ,  Y10T83/0341 ,  Y10T83/0581 ,  Y10T428/12 ,  Y10T428/12361 ,  Y10T428/15 ,  Y10T428/24298 ,  Y10T428/24314 ,  Y10T428/24917

摘要： The invention provides a method for manufacturing printed wiring substrates which can manufacture printed wiring substrates each having resin dielectric layers of uniform thickness and excellent surface flatness while maintaining favorable cutting performance in a dicing step. A multi-printed wiring-substrate panel is manufactured which includes a metal plate having a first main surface and a second main surface, and resin dielectric layers disposed on the first and second main surfaces. The metal plate has first depression portions and second depression portions. The first depression portions are opened at the first main surface and arranged discontinuously along predetermined cutting lines. The second depression portions are opened at the second main surface and arranged discontinuously along the predetermined cutting lines. The multi-printed wiring-substrate panel is cut along the predetermined cutting lines into a plurality of printed wiring substrates.

公开(公告)号：US06872436B2

公开(公告)日：2005-03-29

申请号：US10340031

申请日：2003-01-10

申请人： Tomoe Suzuki ,  Shinji Yuri ,  Kazuhisa Sato ,  Kozo Yamasaki

发明人： Tomoe Suzuki ,  Shinji Yuri ,  Kazuhisa Sato ,  Kozo Yamasaki

IPC分类号： B32B15/08 ,  B32B27/38 ,  H05K1/05 ,  H05K3/00 ,  H05K3/44 ,  B23B3/10

CPC分类号： H05K1/056 ,  B32B15/08 ,  B32B27/38 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0909 ,  H05K2201/09709 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/1572 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49135 ,  Y10T29/49165 ,  Y10T83/0333 ,  Y10T83/0341 ,  Y10T83/0581 ,  Y10T428/12 ,  Y10T428/12361 ,  Y10T428/15 ,  Y10T428/24298 ,  Y10T428/24314 ,  Y10T428/24917

摘要： The invention provides a method for manufacturing printed wiring substrates which can manufacture printed wiring substrates each having resin dielectric layers of uniform thickness and excellent surface flatness while maintaining favorable cutting performance in a dicing step. A multi-printed wiring-substrate panel is manufactured which includes a metal plate having a first main surface and a second main surface, and resin dielectric layers disposed on the first and second main surfaces. The metal plate has first depression portions and second depression portions. The first depression portions are opened at the first main surface and arranged discontinuously along predetermined cutting lines. The second depression portions are opened at the second main surface and arranged discontinuously along the predetermined cutting lines. The multi-printed wiring-substrate panel is cut along the predetermined cutting lines into a plurality of printed wiring substrates.

公开(公告)号：US07742314B2

公开(公告)日：2010-06-22

申请号：US11513034

申请日：2006-08-31

申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Kohki Ogawa

IPC分类号： H05K1/11

CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/40 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0233 ,  H05K1/0234 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wiring board comprising: a board core (11) having a core main surface (12) and a core reverse surface (13); a capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) having a capacitor main surface (102) and a capacitor reverse surface (103) and having a structure in which first inner electrode layers (141) and second inner electrode layers (142) are alternately laminated and arranged via a dielectric layer (105), the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″) being accommodated in the board core (11) in a state in which the core main surface (12) and the capacitor main surface (102) are oriented on a same side; and a wiring laminated portion (31) having a structure in which interlayer insulating layers (33, 35) and conductor layers (42) are alternately laminated on the core main surface (12) and the capacitor main surface (102), wherein an inductor (251, 252, 253) or a resistor (301, 302, 311, 312, 321, 322) is formed on or in the capacitor (101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101J, 1101, 1101′, 1101″, 1101′″, 1101″″, 1101′″″).

摘要翻译： 一种布线板，包括：具有芯主表面（12）和芯反向表面（13）的板芯（11）; 具有电容器主表面的电容器（101,101A，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101,1101,1101“，1101”，1101“”，1101“ 102）和电容器反面（103），并且具有通过电介质层（105）交替层叠配置第一内电极层（141）和第二内电极层（142）的结构，电容器（101,101A ，101B，101C，101D，101E，101F，101G，101H，101J，1101,1101'，1101“，1101”“，1101”“，1101”“）被容纳在板芯（11） 其中所述芯主表面（12）和所述电容器主表面（102）位于同一侧; 以及具有层间绝缘层（33,35）和导体层（42）交替层叠在芯主表面（12）和电容器主表面（102）上的结构的布线层叠部分（31），其中电感器 （101,101A，101B，101C，101D，101E，101F，101G，101H，101J）中的电容器（251,102,253）或电阻器（301,302,311,312,321,322） ，1101,1101'，1101“，1101”“，1101”“，1101”“）。

公开(公告)号：US07473988B2

公开(公告)日：2009-01-06

申请号：US11513249

申请日：2006-08-31

申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Jun Otsuka

IPC分类号： H01L23/495

CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/38 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wiring board includes a substrate core, ceramic capacitors and a built-up layer. The substrate core has a housing opening portion therein which opens at a core main surface. The ceramic capacitors are accommodated in the housing opening portion and oriented such that the core main surface and a capacitor main surface of each capacitor face the same way. The built-up layer includes semiconductor integrated circuit element mounting areas at various locations on a surface thereof. In the substrate core, each ceramic capacitor is respectively disposed in an area corresponding to each semiconductor integrated circuit element mounting area.

摘要翻译： 布线板包括基板芯，陶瓷电容器和积层。 基板芯具有在芯主表面上开口的壳体开口部分。 陶瓷电容器容纳在壳体开口部分中并且取向为使得每个电容器的芯主表面和电容器主表面相同。 积层在其表面上的各个位置包括半导体集成电路元件安装区域。 在基板芯中，每个陶瓷电容器分别设置在对应于每个半导体集成电路元件安装区域的区域中。

公开(公告)号：US20080289866A1

公开(公告)日：2008-11-27

申请号：US11793817

申请日：2005-12-27

申请人： Shinji Yuri ,  Makoto Origuchi ,  Yasuhiko Inui ,  Jun Otsuka

发明人： Shinji Yuri ,  Makoto Origuchi ,  Yasuhiko Inui ,  Jun Otsuka

IPC分类号： H05K1/18 ,  H05K3/36

CPC分类号： H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/15787 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/096 ,  H05K2203/016 ,  H05K2203/0537 ,  Y10T29/49126 ,  H01L2924/00

摘要： A wiring board including a stacked wiring layer portion in which a dielectric layer and a conductor layer are stacked is formed on a core board portion, the stacked wiring layer portion including a stacked composite layer portion in which a polymer dielectric layer, a conductor layer and a ceramic dielectric layer are stacked in this order, the conductor layer being partially cut in the in-plane direction so as to have a conductor side cut portion, the ceramic dielectric layer being partially cut in the in-plane direction so as to have a ceramic side cut portion, the ceramic side cut portion and the conductor side cut portion being communicated to form a communication cut portion, a polymer constituting the polymer dielectric layer being filled in the communication cut portion so as to extend through the conductor side cut portion to the ceramic side cut portion.

摘要翻译： 在芯板部分上形成包括层叠有电介质层和导体层的堆叠布线层部分的布线板，该堆叠布线层部分包括堆叠的复合层部分，其中聚合物介电层，导体层和 陶瓷电介质层按顺序堆叠，导体层在面内方向上被部分地切割成具有导体侧切口部分，陶瓷电介质层在面内方向上被部分地切割，以便具有 陶瓷侧切割部分和导体侧切割部分连通以形成连通切口部分，构成聚合物介电层的聚合物填充在连通切口部分中，以便穿过导体侧切割部分延伸到 陶瓷侧切割部。

公开(公告)号：US20070045814A1

公开(公告)日：2007-03-01

申请号：US11508968

申请日：2006-08-24

申请人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

发明人： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Akifumi Tosa

IPC分类号： H01L23/04

CPC分类号： H01L21/6835 ,  H01G4/236 ,  H01G4/30 ,  H01L21/568 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

摘要翻译： 布线基板包括嵌入其中的基板芯和陶瓷芯片。 基板芯具有在芯主表面处开口的壳体开口部。 陶瓷芯片容纳在壳体开口部分中，使得芯主表面和芯片第一主表面相同。 陶瓷芯片包括多个由金属化层构成的第二端子电极，并且形成在芯片第二主表面上以从其突出。 在芯片第二主表面上形成有从第二主表面侧配置成包围多个第二端子电极的突出部，从而突出。

公开(公告)号：US20060175083A1

公开(公告)日：2006-08-10

申请号：US11350285

申请日：2006-02-09

申请人： Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

发明人： Masaki Muramatsu ,  Shinji Yuri ,  Kazuhiro Urashima ,  Hiroshi Yamamoto ,  Toshitake Seki ,  Motohiko Sato

IPC分类号： H05K1/16

CPC分类号： H01G2/06 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/10 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An intermediate board has a board core formed by a main core body and a sub-core portion. The main core body has a plate-like shape and includes an open sub-core housing portion in which the sub-core portion is housed. A first terminal array of the board core has an area that overlaps an orthogonal projection of the sub-core portion. The latter incorporates a laminated ceramic capacitor formed by first and second conductor layers with a ceramic (dielectric) layer therebetween. The first layer is connected to first and second side terminals of a first type while the second layer is connected to first and second side terminals of a second type. The housing portion has an inner edge which, in cross section, is of a quadrate shape, and a radius portion is formed at each corner having a dimension of between 0.1 and 2 mm.

摘要翻译： 中间板具有由主芯体和副芯部形成的板芯。 主芯体具有板状形状，并且包括其中容纳有副芯部的开放子芯容纳部。 板芯的第一端子阵列具有与子芯部的正交突起重叠的区域。 后者包括由其间具有陶瓷（电介质）层的第一和第二导体层形成的层叠陶瓷电容器。 第一层连接到第一类型的第一和第二侧端子，而第二层连接到第二类型的第一和第二侧端子。 壳体部分具有横截面为正方形的内边缘，并且在每个拐角处形成具有0.1至2mm的尺寸的半径部分。

公开(公告)号：US08863378B2

公开(公告)日：2014-10-21

申请号：US12706695

申请日：2010-02-16

申请人： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

发明人： Masaki Muramatsu ,  Shinji Yuri ,  Makoto Origuchi ,  Kazuhiro Urashima

IPC分类号： H01K3/10 ,  H01L23/50 ,  H05K1/02 ,  H01L23/00 ,  H05K1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H05K1/11 ,  H05K1/16 ,  H05K1/14 ,  H05K3/46

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/142 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/10674 ,  H05K2201/10712 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for manufacturing a wiring board including, as steps executed in written order: a sub-core accommodation step of accommodating the ceramic sub-core in the sub-core accommodation space through the first-major-surface-side opening of the sub-core accommodation space; and a film formation and charging step of forming a lowest resin insulating layer of the first-major-surface-side wiring laminate by sticking a resin material to the core body and the ceramic sub-core from the first major surface side, and forming a groove-filling portion that is continuous with the lowest resin insulating layer by charging the resin material into a gap between the core body and the ceramic sub-core.

摘要翻译： 一种布线板的制造方法，其特征在于，具有以下顺序执行的步骤：副芯放置步骤，通过所述副芯容纳空间中的所述子芯容纳空间的第一主表面侧开口容纳所述陶瓷副芯， 核心住宿空间; 以及成膜和充电步骤，通过从第一主表面侧将树脂材料粘附到芯体和陶瓷副芯，形成第一主表面侧布线层压体的最低树脂绝缘层，并形成 通过将树脂材料充填到芯体和陶瓷子芯之间的间隙中，与最低树脂绝缘层连续的凹槽填充部分。

公开(公告)号：US07889509B2

公开(公告)日：2011-02-15

申请号：US11513039

申请日：2006-08-31

申请人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

发明人： Kazuhiro Urashima ,  Shinji Yuri ,  Manabu Sato ,  Yasuhiro Sugimoto

IPC分类号： H05K7/00

CPC分类号： H05K1/185 ,  H01G2/06 ,  H01G4/385 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K3/4602 ,  H05K2201/10045 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

摘要： A circuit board (10, 10″, 10′″) comprising: a board core (11) having a main core surface (12) and a rear core surface (13); a ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) having a main capacitor surface (102) and a rear capacitor surface (103), having a structure in which a first inner electrode layer (141) and a second inner electrode layer (142) are alternately stacked with a ceramic dielectric layer (105) interposed therebetween, and having a plurality of capacitor function units (107, 108) being electrically independent from each other, the ceramic capacitor (101, 101′, 101″, 101′″, 101″″, 101″″′, 101″″″) being buried in the board core (11) in a state where the main core surface (12) and the main capacitor surface (102) are directed in a same direction; and a buildup layer (31) having a structure in which an interlayer insulating layer (33, 35) and a conductor layer (42) are alternately stacked on the main core surface (12) and the main capacitor surface (102) and having a semiconductor integrated circuit device mounting region (23, 51, 52) for mounting a semiconductor integrated circuit device (21, 53, 54) having a plurality of processor cores (24, 25) on a surface (39) of the buildup layer (31), wherein the plurality of capacitor function units (107, 108) are capable of being electrically connected to the plurality of processor cores (24, 25), respectively.

摘要翻译： 一种电路板（10,10“，10”），包括：具有主芯表面（12）和后芯表面（13）的板芯（11）; 具有主电容器表面（102）和后电容器表面（103）的陶瓷电容器（101,101'，101“，101”，101“”，101“”，101“”“）， 其中第一内部电极层（141）和第二内部电极层（142）交替层叠有介于其间的陶瓷介电层（105），并且具有多个电容器功能单元（107,108），其电独立于 相互之间的陶瓷电容器（101,101'，101“，101”，101“，101”，101“”101“”）被埋在板芯11中， （12）和主电容器表面（102）指向相同的方向; 以及具有层间绝缘层（33,35）和导体层（42）在主芯面（12）和主电容器表面（102）上交替层叠的结构的积层（31），具有 半导体集成电路器件安装区域（23,51,52），用于安装具有多个处理器核心（24,25）的半导体集成电路器件（21,53,54），所述多个处理器核心（24,25）在所述生成层（31）的表面（39）上 ），其中所述多个电容器功能单元（107,108）能够分别电连接到所述多个处理器核（24,25）。