公开(公告)号：US20060049995A1

公开(公告)日：2006-03-09

申请号：US11215131

申请日：2005-08-31

申请人： Toshikazu Imaoka ,  Sawai Tetsuro ,  Atsushi Sakai ,  Ryosuke Usui ,  Yasunori Inoue

发明人： Toshikazu Imaoka ,  Sawai Tetsuro ,  Atsushi Sakai ,  Ryosuke Usui ,  Yasunori Inoue

IPC分类号： H01Q1/24

CPC分类号： H01Q1/2283 ,  H01L24/24 ,  H01L24/45 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73267 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/22 ,  H05K1/0298 ,  H05K1/16 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated antenna type circuit apparatus which provides excellent circuit characteristics while suppressing an increase in packaging area. The integrated antenna type circuit apparatus includes an insulating base, a semiconductor circuit device, chip parts, a molding resin, an antenna conductor, a ground conductor, and external lead electrodes. The plurality of chip parts are mounted on the insulating base, and are soldered to electrodes of wiring conductors on the top of the insulating base for electric and physical connection. The insulating base has a multilayer structure, being formed by laminating a plurality of insulator layers. The antenna conductor is formed on the bottom of the insulating base. A wiring conductor adjacent to the antenna conductor is provided with the ground conductor so that it overlaps with the antenna conductor.

公开(公告)号：US20070176303A1

公开(公告)日：2007-08-02

申请号：US11645803

申请日：2006-12-27

申请人： Makoto Murai ,  Ryosuke Usui ,  Tetsuro Sawai ,  Toshikazu Imaoka ,  Yasunori Inoue

发明人： Makoto Murai ,  Ryosuke Usui ,  Tetsuro Sawai ,  Toshikazu Imaoka ,  Yasunori Inoue

IPC分类号： H01L23/28

CPC分类号： H01L23/3107 ,  H01L21/4832 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/16 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/85001 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A highly reliable circuit device is provided at low cost. The circuit device includes a semiconductor element electrically connected to a wiring layer (copper plate and plating film) and passive parts sealed by a molded resin layer. The wiring layer has a predetermined pattern formed by a conductive member. The molded resin layer has projections protruding from gaps in the adjacent wiring layer toward an underside of the wiring layer. Thereby, the drop of yield is prevented and the highly reliable circuit device is provided at low cost.

摘要翻译： 以低成本提供了高度可靠的电路装置。 电路装置包括与布线层（铜板和电镀膜）电连接的半导体元件和由模制树脂层密封的被动部分。 布线层具有由导电构件形成的预定图案。 模制树脂层具有从相邻布线层中的间隙朝向布线层的下侧突出的突起。 从而，可以防止产量的下降，并且以低成本提供高可靠性的电路装置。

公开(公告)号：US07875980B2

公开(公告)日：2011-01-25

申请号：US11215121

申请日：2005-08-31

申请人： Toshikazu Imaoka ,  Ryosuke Usui

发明人： Toshikazu Imaoka ,  Ryosuke Usui

IPC分类号： H01L23/12

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/183 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4644 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed by laminating a plurality of insulator films. The semiconductor chip and the chip component are mounted on the base and embedded in the insulating base. A recess is formed on the surface of the semiconductor device and reaches down to any of wiring conductor layers. The semiconductor chip and the chip component are mounted on the recess.

摘要翻译： 提供了一种用于减小半导体器件的尺寸的技术。 半导体器件包括基底，半导体芯片，芯片部件，绝缘基底，布线图案，通孔塞，外部引出电极，凹部和树脂。 绝缘基底具有通过层叠多个绝缘膜形成的多层结构。 半导体芯片和芯片组件安装在基座上并嵌入绝缘基座中。 在半导体器件的表面上形成凹部，并且到达布线导体层中的任何一个。 半导体芯片和芯片组件安装在凹槽上。

公开(公告)号：US20060043606A1

公开(公告)日：2006-03-02

申请号：US11215121

申请日：2005-08-31

申请人： Toshikazu Imaoka ,  Ryosuke Usui

发明人： Toshikazu Imaoka ,  Ryosuke Usui

IPC分类号： H01L23/48

CPC分类号： H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/183 ,  H05K1/185 ,  H05K3/284 ,  H05K3/4644 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technique for reducing the size of a semiconductor device is provided. A semiconductor device comprises a base, a semiconductor chip, a chip component, an insulating base, a wiring pattern, a via plug, an external lead-out electrode, a recess, and a resin. The insulating base has a multi-layer structure formed by laminating a plurality of insulator films. The semiconductor chip and the chip component are mounted on the base and embedded in the insulating base. A recess is formed on the surface of the semiconductor device and reaches down to any of wiring conductor layers. The semiconductor chip and the chip component are mounted on the recess.

摘要翻译： 提供了一种用于减小半导体器件的尺寸的技术。 半导体器件包括基底，半导体芯片，芯片部件，绝缘基底，布线图案，通孔塞，外部引出电极，凹部和树脂。 绝缘基底具有通过层叠多个绝缘膜形成的多层结构。 半导体芯片和芯片组件安装在基座上并嵌入绝缘基座中。 在半导体器件的表面上形成凹部，并且到达布线导体层中的任何一个。 半导体芯片和芯片组件安装在凹槽上。

公开(公告)号：US20050067712A1

公开(公告)日：2005-03-31

申请号：US10951214

申请日：2004-09-27

申请人： Toshikazu Imaoka ,  Ryosuke Usui ,  Atsushi Nakano ,  Atsushi Kato

发明人： Toshikazu Imaoka ,  Ryosuke Usui ,  Atsushi Nakano ,  Atsushi Kato

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L2224/48237 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor apparatus includes a first conductive film and a second conductive film provided on respective sides of an insulating resin film. A circuit element is mounted on the second conductive film. The circuit element is electrically connected to the second conductive film. The second conductive film is provided to cover a via plug. The via plug is tapered with a progressively smaller diameter toward the second conductive film and away from the first conductive film.

摘要翻译： 半导体装置包括设置在绝缘树脂膜的两侧的第一导电膜和第二导电膜。 电路元件安装在第二导电膜上。 电路元件电连接到第二导电膜。 第二导电膜被设置成覆盖通孔塞。 通孔塞逐渐变细，朝向第二导电膜逐渐变小，并远离第一导电膜。

公开(公告)号：US20050212146A1

公开(公告)日：2005-09-29

申请号：US11054039

申请日：2005-02-08

申请人： Toshikazu Imaoka ,  Takeshi Yamaguchi ,  Ryosuke Usui ,  Hiroyuki Watanabe ,  Toshimichi Naruse ,  Atsushi Kato

发明人： Toshikazu Imaoka ,  Takeshi Yamaguchi ,  Ryosuke Usui ,  Hiroyuki Watanabe ,  Toshimichi Naruse ,  Atsushi Kato

IPC分类号： H01L23/28 ,  H01L21/44 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor pellet and chip components are provided on an insulating substrate, and are sealed with a molding resin that is molded by transfer molding. The chip components are positioned so as to surround the semiconductor pellet on all four sides. The lengthwise directions of the chip components surrounding the semiconductor pellet are aligned in a uniform direction. The insulating substrate is set within a die molding apparatus so that during resin injection, the lengthwise directions of the chip components are aligned substantially perpendicularly to the direction of flow of the injected resin.

摘要翻译： 半导体芯片和芯片部件设置在绝缘基板上，并用通过传递模塑成型的模制树脂密封。 芯片部件被定位成围绕半导体芯片四周。 围绕半导体芯片的芯片部件的长度方向在均匀的方向上排列。 将绝缘基板设置在模具成型装置内，使得在树脂注入期间，芯片部件的长度方向基本上垂直于注入树脂的流动方向排列。

公开(公告)号：US07709941B2

公开(公告)日：2010-05-04

申请号：US11054039

申请日：2005-02-08

申请人： Toshikazu Imaoka ,  Takeshi Yamaguchi ,  Ryosuke Usui ,  Hiroyuki Watanabe ,  Toshimichi Naruse ,  Atsushi Kato

发明人： Toshikazu Imaoka ,  Takeshi Yamaguchi ,  Ryosuke Usui ,  Hiroyuki Watanabe ,  Toshimichi Naruse ,  Atsushi Kato

IPC分类号： H01L23/02

CPC分类号： H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor pellet and chip components are provided on an insulating substrate, and are sealed with a molding resin that is molded by transfer molding. The chip components are positioned so as to surround the semiconductor pellet on all four sides. The lengthwise directions of the chip components surrounding the semiconductor pellet are aligned in a uniform direction. The insulating substrate is set within a die molding apparatus so that during resin injection, the lengthwise directions of the chip components are aligned substantially perpendicularly to the direction of flow of the injected resin.

摘要翻译： 半导体芯片和芯片部件设置在绝缘基板上，并用通过传递模塑成型的模制树脂密封。 芯片部件被定位成围绕半导体芯片四周。 围绕半导体芯片的芯片部件的长度方向在均匀的方向上排列。 将绝缘基板设置在模具成型装置内，使得在树脂注入期间，芯片部件的长度方向基本上垂直于注入树脂的流动方向排列。

公开(公告)号：US20060238961A1

公开(公告)日：2006-10-26

申请号：US11391680

申请日：2006-03-29

申请人： Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai ,  Yasunori Inoue

发明人： Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai ,  Yasunori Inoue

IPC分类号： H02B1/00

CPC分类号： H01L23/50 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48237 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.

摘要翻译： 降低了在具有多堆叠结构的电路装置中的电路元件之间传播的接地噪声。 设置在第二电路元件的表面上的接地焊盘通过诸如金的接地线连接到设置在导电层的表面上的接合线。 设置在导电层的表面上的接合焊盘通过诸如金的接地线连接到设置在接地线上的引线。 该结构在第二电路元件和导电层之间产生电容，以防止噪声电路从元件传播到接地布线。

公开(公告)号：US07453153B2

公开(公告)日：2008-11-18

申请号：US11391680

申请日：2006-03-29

申请人： Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai ,  Yasunori Inoue

发明人： Atsushi Saita ,  Toshikazu Imaoka ,  Tetsuro Sawai ,  Yasunori Inoue

IPC分类号： H01L23/552 ,  H01L23/34

CPC分类号： H01L23/50 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48237 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/4943 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： The ground noise is reduced which propagates between circuit elements in a circuit device having a multiple stack structure. A grounding bonding pad provided on the surface of a second circuit element is connected to a bonding wire provided on the surface of a conduction layer via a grounding wire such as gold. A bonding pad provided on the surface of the conductive layer is connected to a lead provided on a ground wire via a grounding wire such as gold. This structure creates a capacitance between the second circuit element and the conduction layer so as to prevent the propagation of noise circuit from element to the ground wiring.

摘要翻译： 降低了在具有多堆叠结构的电路装置中的电路元件之间传播的接地噪声。 设置在第二电路元件的表面上的接地焊盘通过诸如金的接地线连接到设置在导电层的表面上的接合线。 设置在导电层的表面上的接合焊盘通过诸如金的接地线连接到设置在接地线上的引线。 该结构在第二电路元件和导电层之间产生电容，以防止噪声电路从元件传播到接地布线。

公开(公告)号：US07893539B2

公开(公告)日：2011-02-22

申请号：US12022840

申请日：2008-01-30

申请人： Takeshi Otsuka ,  Toshikazu Imaoka

发明人： Takeshi Otsuka ,  Toshikazu Imaoka

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor apparatus includes: a wiring board; a first semiconductor device mounted on the wiring board; a second semiconductor device which is stacked on the first semiconductor device and a projection part projects from the outer edge of the first semiconductor device; and a sealing resin layer which seals each semiconductor device. And the second semiconductor device has thereon a first analog cell, and a second analog cell which reaches a higher temperature than the first analog cell, and the second analog cell is arranged so as to include the projection part of the second semiconductor device.

摘要翻译： 一种半导体装置，包括：布线板; 安装在所述布线板上的第一半导体器件; 堆叠在第一半导体器件上的第二半导体器件和从第一半导体器件的外边缘突出的突出部分; 以及密封每个半导体器件的密封树脂层。 并且第二半导体器件具有第一模拟单元和达到比第一模拟单元更高温度的第二模拟单元，并且第二模拟单元布置成包括第二半导体器件的突出部分。