公开(公告)号：US08476770B2

公开(公告)日：2013-07-02

申请号：US13178345

申请日：2011-07-07

申请人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

发明人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

IPC分类号： H01L23/48

CPC分类号： H01L21/76802 ,  B29C43/04 ,  B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/19 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/83005

摘要： Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed.

摘要翻译： 公开了用于在集成电路封装中形成通孔的方法和装置。 公开了一种装置，其具有一个基板，该基板具有一个或多个接合焊盘端子，用于在至少一个表面上接收电连接; 覆盖所述衬底的所述至少一个表面并具有第一厚度的封装层; 多个通孔，其延伸穿过所述封装层并且与所述一个或多个接合焊盘端子中的至少一个相对应地定位; 导体材料设置在所述多个通孔内，以在所述多个通孔内形成电连接器; 以及设置在所述封装层的表面上的至少一个外部端子，通过所述多个通孔中的至少一个通孔中的电连接器电耦合到所述一个或多个接合焊盘端子中的一个。 公开了通孔的封装结构和方法。

公开(公告)号：US20130009319A1

公开(公告)日：2013-01-10

申请号：US13178345

申请日：2011-07-07

申请人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

发明人： Tung-Liang Shao ,  Chih-Hang Tung ,  Chen-Hua Yu ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Da-Yuan Shih

IPC分类号： H01L23/48 ,  B29C43/04 ,  H01L21/56

CPC分类号： H01L21/76802 ,  B29C43/04 ,  B29C43/18 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/19 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/83005

摘要： Methods and apparatus for forming through vias in an integrated circuit package are disclosed. An apparatus is disclosed, having a substrate having one or more bond pad terminals for receiving electrical connections on at least one surface; an encapsulation layer covering the at least one surface of the substrate and having a first thickness; a plurality of through vias extending through the encapsulation layer and positioned in correspondence with at least one of the one or more bond pad terminals; conductor material disposed within the plurality of through vias to form electrical connectors within the plurality of through vias; and at least one external terminal disposed on a surface of the encapsulation layer, electrically coupled to one of the one or more bond pad terminals by an electrical connector in at least one of the plurality of through vias. Package arrangements and methods for the through vias are disclosed.

摘要翻译： 公开了用于在集成电路封装中形成通孔的方法和装置。 公开了一种装置，其具有一个基板，该基板具有一个或多个接合焊盘端子，用于在至少一个表面上接收电连接; 覆盖所述衬底的所述至少一个表面并具有第一厚度的封装层; 多个通孔，其延伸穿过所述封装层并且与所述一个或多个接合焊盘端子中的至少一个相对应地定位; 导体材料设置在所述多个通孔内，以在所述多个通孔内形成电连接器; 以及设置在所述封装层的表面上的至少一个外部端子，通过所述多个通孔中的至少一个通孔中的电连接器电耦合到所述一个或多个接合焊盘端子中的一个。 公开了通孔的封装结构和方法。

公开(公告)号：US20120092033A1

公开(公告)日：2012-04-19

申请号：US12903984

申请日：2010-10-13

申请人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： G01R31/00 ,  G01R27/00 ,  G01R29/26

CPC分类号： G01R31/2648 ,  G01R31/002 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2224/13

摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

摘要翻译： 提供了一种用于测试未封装的半导体晶片的测试结构。 测试结构包括耦合到半导体晶片的互连结构的施力部件。 力施加部件可操作以向半导体晶片施加力。 测试结构还包括耦合到互连结构的第一和第二测试部分。 第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。 第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

公开(公告)号：US08618827B2

公开(公告)日：2013-12-31

申请号：US12903984

申请日：2010-10-13

申请人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

发明人： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2648 ,  G01R31/002 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2224/13

摘要： Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

摘要翻译： 提供了一种用于测试未封装的半导体晶片的测试结构。 测试结构包括耦合到半导体晶片的互连结构的施力部件。 力施加部件可操作以向半导体晶片施加力。 测试结构还包括耦合到互连结构的第一和第二测试部分。 第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。 第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

公开(公告)号：US08754514B2

公开(公告)日：2014-06-17

申请号：US13206694

申请日：2011-08-10

申请人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L23/02 ,  H01L21/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L25/065

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83005

摘要： A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

摘要翻译： 多芯片晶片级封装包括三个堆叠的半导体管芯。 第一半导体管芯被嵌入在第一光敏材料层中。 第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。 第三半导体管芯背靠背连接到第二半导体管芯。 第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。 多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

公开(公告)号：US20130037950A1

公开(公告)日：2013-02-14

申请号：US13206694

申请日：2011-08-10

申请人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

发明人： Chun Hui Yu ,  Chih-Hang Tung ,  Tung-Liang Shao ,  Chen-Hua Yu ,  Da-Yuan Shih

IPC分类号： H01L23/485 ,  H01L21/82 ,  H01L21/56

CPC分类号： H01L23/481 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8203 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/83005

摘要： A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

摘要翻译： 多芯片晶片级封装包括三个堆叠的半导体管芯。 第一半导体管芯被嵌入在第一光敏材料层中。 第二半导体管芯堆叠在第一半导体管芯的顶部上，其中第二半导体管芯与第一半导体管芯面对面连接。 第三半导体管芯背靠背连接到第二半导体管芯。 第二半导体管芯和第三半导体管芯都嵌入第二光敏材料层。 多芯片晶片级封装还包括形成在第一光敏材料层和第二光敏材料层中的多个通过组装通孔。

公开(公告)号：US20120018875A1

公开(公告)日：2012-01-26

申请号：US12840900

申请日：2010-07-21

申请人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

发明人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L23/498

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/93 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

摘要翻译： 模具包括金属焊盘，钝化层和钝化层上的图案化缓冲层。 图案化缓冲层包括彼此分离的多个离散部分。 在图案化缓冲层的开口和钝化层中的开口上形成凸块下冶金（UBM）。 在UBM上形成电耦合的金属凸块。

公开(公告)号：US08610267B2

公开(公告)日：2013-12-17

申请号：US12840900

申请日：2010-07-21

申请人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

发明人： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L23/48

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/93 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

公开(公告)号：US08531032B2

公开(公告)日：2013-09-10

申请号：US13224487

申请日：2011-09-02

申请人： Chen-Hua Yu ,  Chih-Hang Tung ,  Tung-Liang Shao

发明人： Chen-Hua Yu ,  Chih-Hang Tung ,  Tung-Liang Shao

IPC分类号： H01L23/498

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49816 ,  H01L23/5329 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/15321 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/181 ,  H01L2924/00

摘要： A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.

公开(公告)号：US20130056871A1

公开(公告)日：2013-03-07

申请号：US13224487

申请日：2011-09-02

申请人： Chen-Hua Yu ,  Chih-Hang Tung ,  Tung-Liang Shao

发明人： Chen-Hua Yu ,  Chih-Hang Tung ,  Tung-Liang Shao

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/49816 ,  H01L23/5329 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/15321 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/181 ,  H01L2924/00

摘要： A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.