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36 条记录 (耗时 0.032 秒)

    Tray for ball grid array devices
    6.
    发明授权
    Tray for ball grid array devices 有权
    球栅阵列装置托盘

    公开(公告)号：US6116427A

    公开(公告)日：2000-09-12

    申请号：US494891

    申请日：2000-01-31

    申请人： Chung-Ju Wu ,  Wei-Feng Lin ,  Chen-Wen Tsai

    发明人： Chung-Ju Wu ,  Wei-Feng Lin ,  Chen-Wen Tsai

    IPC分类号： H01L21/673 ,  H05K13/00 ,  B65D73/02

    CPC分类号： H01L21/67333 ,  H05K13/0084

    摘要： A tray is adapted to receive a plurality of ball grid array devices therein, and includes a base plate having a device-receiving portion and a peripheral portion around the device-receiving portion. The device-receiving portion has a top side formed with a device-receiving recess. The top side of the device-receiving portion is further formed with a partition unit in the device-receiving recess for dividing the device-receiving recess into a plurality of cavities adapted for receiving the ball grid array devices respectively therein. The device-receiving portion further has a bottom side formed with a plurality of openings. Each of the openings is aligned with a corresponding one of the cavities and is adapted to receive an array of ball contacts formed on a bottom side of the ball grid array device that is disposed in the corresponding one of the cavities therein. The openings are grouped into a set of first openings remote from the peripheral portion and a set of second openings surrounding the first openings and adjacent to the peripheral portion. Guard strips are formed on the bottom side of the device-receiving portion and are disposed solely and respectively in the second openings.

    摘要翻译： 托盘适于在其中容纳多个球栅阵列器件，并且包括具有器件接收部分和围绕器件接收部分的周边部分的基板。 装置接收部分具有形成有装置容纳凹部的顶侧。 装置接收部分的顶侧还在装置容纳凹槽中形成有分隔单元，用于将装置容纳凹槽分成适于分别容纳球栅阵列装置的多个空腔。 装置接收部还具有形成有多个开口的底侧。 每个开口与相应的一个空腔对准，并且适于接收形成在球栅阵列器件的底侧上的球形触点阵列，其布置在其中的相应的一个空腔中。 开口被分组成远离周边部分的一组第一开口和围绕第一开口并且邻近周边部分的一组第二开口。 保护条形成在装置接收部分的底侧上，并且分别单独设置在第二开口中。

    Chip-packaging substrate
    7.
    发明授权
    Chip-packaging substrate 失效
    芯片封装基板

    公开(公告)号：US06838756B2

    公开(公告)日：2005-01-04

    申请号：US10227266

    申请日：2002-08-26

    申请人： Wei-Feng Lin ,  Chung-Ju Wu ,  Chen-Wen Tsai

    发明人： Wei-Feng Lin ,  Chung-Ju Wu ,  Chen-Wen Tsai

    IPC分类号： H01L23/13 ,  H01L23/495

    CPC分类号： H01L23/13 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chip-packaging substrate. The substrate is capable of reducing damage during packaging, shrinking its connecting portions so that the length of any of the gap slots between the packaging portion and the frame portion of the substrate is increased. Furthermore, a dummy layer is provided to one surface of the frame portion to flush the surface on the frame portion with that of the packaging portion as much as possible.

    摘要翻译： 芯片封装基板。 该基板能够减少封装期间的损坏，使其连接部分收缩，使得封装部分和基板的框架部分之间的任何间隙的长度增加。 此外，在框架部分的一个表面上设置虚拟层，以尽可能多地将框架部分的表面与包装部分的表面齐平。

    Integrated circuit bonding device and manufacturing method thereof
    9.
    发明授权
    Integrated circuit bonding device and manufacturing method thereof 有权
    集成电路接合装置及其制造方法

    公开(公告)号：US06765301B2

    公开(公告)日：2004-07-20

    申请号：US10212106

    申请日：2002-08-06

    申请人： Chung-Ju Wu ,  Kuei-Chen Liang ,  Wei-Feng Lin

    发明人： Chung-Ju Wu ,  Kuei-Chen Liang ,  Wei-Feng Lin

    IPC分类号： H01L2348

    CPC分类号： H01L23/49838 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2224/05599

    摘要： An integrated circuit device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the substrate. There are a signal pad and two shielding pads set at the two sides of the signal pad on the edge of the chip. The signal wire bonding is coupled to the signal connection point and the signal pad. Two shielding wire bondings are coupled to the shielding connection points and the shielding pads and extend along both sides of the signal wire bonding. The signal trace line is set on the substrate and coupled to the signal connection point. The power ring circuit is set on the substrate and coupled to the shielding connection points. The power circuit includes two shielding lines extending along both sides of the signal trace line.

    摘要翻译： 集成电路器件。 基板包括设置在信号连接点两侧的信号连接点和两个屏蔽连接点。 芯片设置在基板上。 信号焊盘和两个屏蔽焊盘设置在芯片边缘的信号焊盘两侧。 信号线接合耦合到信号连接点和信号焊盘。 两个屏蔽线接合耦合到屏蔽连接点和屏蔽焊盘，并沿着信号线接合的两侧延伸。 信号跟踪线设置在基板上并耦合到信号连接点。 电源环电路设置在基板上并耦合到屏蔽连接点。 电源电路包括沿着信号迹线的两侧延伸的两条屏蔽线。

    Thermal dissipating element of a chip
    10.
    发明申请
    Thermal dissipating element of a chip 审中-公开
    芯片的散热元件

    公开(公告)号：US20050093136A1

    公开(公告)日：2005-05-05

    申请号：US10698476

    申请日：2003-11-03

    申请人： Wei-Chi Liu ,  Wei-Feng Lin ,  Chung-Ju Wu

    发明人： Wei-Chi Liu ,  Wei-Feng Lin ,  Chung-Ju Wu

    IPC分类号： H01L23/10 ,  H01L23/433

    CPC分类号： H01L23/4334 ,  H01L2224/49175 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012

    摘要： The present invention relates to a thermal dissipating element of a chip to dissipate heat producing by operating the chip. The thermal dissipating element includes a cover and a lump. The cover includes a top plate and a side plate, wherein the top plate curves and extendedly connects to the side plate. The lump is fastened between the chip and the top plate of the cover.

    摘要翻译： 本发明涉及一种芯片的散热元件，用于散发通过操作芯片产生的热量。 散热元件包括盖和块。 该盖包括顶板和侧板，其中顶板弯曲并且延伸地连接到侧板。 该块被固定在芯片和盖板的顶板之间。