公开(公告)号：US08674212B2

公开(公告)日：2014-03-18

申请号：US12014356

申请日：2008-01-15

申请人： William Hullinger Huber ,  Charles Stephen Korman ,  Raymond Albert Fillion ,  Anil Raj Duggal ,  William Edward Burdick, Jr.

发明人： William Hullinger Huber ,  Charles Stephen Korman ,  Raymond Albert Fillion ,  Anil Raj Duggal ,  William Edward Burdick, Jr.

IPC分类号： H01L31/0203

CPC分类号： H01L24/95 ,  H01L31/048 ,  H01L2224/95144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/0106 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  Y02E10/50 ,  H01L2924/00

摘要： An assembly is provided and includes at least one solar cell comprising a photovoltaic element having an upper surface for receiving and absorbing radiation, a lower surface for coupling to an article, a first end and a second end. The solar cell further includes at least one magnet attached to the first end of the photovoltaic element. The assembly further includes an article comprising a substrate, and a magnetic film disposed on the substrate and defining at least one receptor site. Each solar cell is disposed at a respective receptor site.

摘要翻译： 提供一种组件，并且包括至少一个太阳能电池，其包括具有用于接收和吸收辐射的上表面的光伏元件，用于耦合到制品的下表面，第一端和第二端。 太阳能电池还包括附接到光伏元件的第一端的至少一个磁体。 组件还包括包含衬底的物品和设置在衬底上并限定至少一个受体位点的磁性膜。 每个太阳能电池设置在相应的受体部位。

公开(公告)号：US20090178709A1

公开(公告)日：2009-07-16

申请号：US12014356

申请日：2008-01-15

申请人： William Hullinger Huber ,  Charles Stephen Korman ,  Raymond Albert Fillion ,  Anil Raj Duggal ,  William Edward Burdick, JR.

发明人： William Hullinger Huber ,  Charles Stephen Korman ,  Raymond Albert Fillion ,  Anil Raj Duggal ,  William Edward Burdick, JR.

IPC分类号： H01L31/028 ,  H01L31/04

CPC分类号： H01L24/95 ,  H01L31/048 ,  H01L2224/95144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01056 ,  H01L2924/0106 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/15788 ,  Y02E10/50 ,  H01L2924/00

摘要： An assembly is provided and includes at least one solar cell comprising a photovoltaic element having an upper surface for receiving and absorbing radiation, a lower surface for coupling to an article, a first end and a second end. The solar cell further includes at least one magnet attached to the first end of the photovoltaic element. The assembly further includes an article comprising a substrate, and a magnetic film disposed on the substrate and defining at least one receptor site. Each solar cell is disposed at a respective receptor site.

摘要翻译： 提供一种组件，并且包括至少一个太阳能电池，其包括具有用于接收和吸收辐射的上表面的光伏元件，用于耦合到制品的下表面，第一端和第二端。 太阳能电池还包括附接到光伏元件的第一端的至少一个磁体。 组件还包括包含衬底的物品和设置在衬底上并限定至少一个受体位点的磁性膜。 每个太阳能电池设置在相应的受体部位。

公开(公告)号：US5946546A

公开(公告)日：1999-08-31

申请号：US218639

申请日：1998-12-22

申请人： Raymond Albert Fillion ,  William Edward Burdick, Jr.

发明人： Raymond Albert Fillion ,  William Edward Burdick, Jr.

IPC分类号： G01R1/04 ,  G01R31/28 ,  H01L21/66

CPC分类号： G01R31/2863 ,  G01R1/04 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011

摘要： A burn-in frame having at least one window and including resistors having resistor pads is situated on a flexible layer, and at least one integrated circuit chip having chip pads is situated in the at least one window. Via openings are formed in the flexible layer to extend to the chip pads and the resistor pads. A pattern of electrical conductors is applied over the flexible layer and extending into the vias. The at least one integrated circuit chip is burned in. The burn-in frame may further include fuses, frame contacts, and voltage bias tracks. After burning in the at least one integrated circuit chip, the chip pads can be electrically isolated and the at least one integrated circuit chip can be tested. This method can also be used to burn-in and test multichip modules.

摘要翻译： 具有至少一个窗口并且包括具有电阻器焊盘的电阻器的老化框架位于柔性层上，并且至少一个具有芯片焊盘的集成电路芯片位于该至少一个窗口中。 在柔性层中形成通孔以延伸到芯片焊盘和电阻焊盘。 电导体的图案施加在柔性层上并延伸到通孔中。 该至少一个集成电路芯片被烧毁。老化框架还可以包括熔断器，框架触点和电压偏置轨道。 在至少一个集成电路芯片中燃烧之后，芯片焊盘可以是电隔离的，并且可以测试至少一个集成电路芯片。 该方法也可用于老化和测试多芯片模块。

公开(公告)号：US5888837A

公开(公告)日：1999-03-30

申请号：US632858

申请日：1996-04-16

申请人： Raymond Albert Fillion ,  William Edward Burdick, Jr.

发明人： Raymond Albert Fillion ,  William Edward Burdick, Jr.

IPC分类号： G01R1/04 ,  G01R31/28 ,  H01L21/66

CPC分类号： G01R31/2863 ,  G01R1/04 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011

摘要： A burn-in frame having at least one window and including resistors having resistor pads is situated on a flexible layer, and at least one integrated circuit chip having chip pads is situated in the at least one window. Via openings are formed in the flexible layer to extend to the chip pads and the resistor pads. A pattern of electrical conductors is applied over the flexible layer and extending into the vias. The at least one integrated circuit chip is burned in. The burn-in frame may further include fuses, frame contacts, and voltage bias tracks. After burning in the at least one integrated circuit chip, the chip pads can be electrically isolated and the at least one integrated circuit chip can be tested. This method can also be used to burn-in and test multichip modules.

公开(公告)号：US06242282B1

公开(公告)日：2001-06-05

申请号：US09411101

申请日：1999-10-04

申请人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2144

CPC分类号： H01L24/48 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/24227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

公开(公告)号：US06396153B2

公开(公告)日：2002-05-28

申请号：US09768598

申请日：2001-01-25

申请人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

发明人： Raymond Albert Fillion ,  Ernest Wayne Balch ,  Ronald Frank Kolc ,  William Edward Burdick, Jr. ,  Robert John Wojnarowski ,  Leonard Richard Douglas ,  Thomas Bert Gorczyca

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/24227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2224/92144 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

摘要翻译： 一种用于封装至少一个电路芯片的方法包括：提供包括具有第一侧和第二侧的绝缘材料的互连层，在第二侧的第二侧金属化部分上而不是在第二侧非金属化部分上图案化的初始金属化 第二侧，至少一个从第一侧延伸到第二侧金属化部分之一的衬底通孔;以及至少一个芯片通孔，其从第一侧延伸到第二侧非金属化部分之一; 将所述至少一个电路芯片定位在所述第二侧上，所述至少一个电路芯片的至少一个芯片焊盘与所述至少一个芯片通孔对准; 以及在所述互连层的第一侧和所述通孔的选定部分上图案化连接金属化，以便延伸到所述至少一个第二侧金属化部分和所述至少一个芯片焊盘。 在相关实施例中，通孔被预先金属化并且通过导电粘合剂耦合到电路芯片的芯片焊盘。 薄膜无源元件和多层互连可另外包含在封装中。

公开(公告)号：US06239482B1

公开(公告)日：2001-05-29

申请号：US09334572

申请日：1999-06-21

申请人： Raymond Albert Fillion ,  William Edward Burdick, Jr. ,  Ronald Frank Kolc ,  James Wilson Rose ,  Glenn Scott Claydon

发明人： Raymond Albert Fillion ,  William Edward Burdick, Jr. ,  Ronald Frank Kolc ,  James Wilson Rose ,  Glenn Scott Claydon

IPC分类号： H01L2302

CPC分类号： H01L24/25 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

摘要： An integrated circuit package includes at least one integrated circuit element coupled to a polymer film; a window frame coupled to the polymer film and surrounding the at least one integrated circuit element; and encapsulant material positioned between the at least one integrated circuit element and the window frame.

摘要翻译： 集成电路封装包括耦合到聚合物膜的至少一个集成电路元件; 耦合到所述聚合物膜并围绕所述至少一个集成电路元件的窗框; 以及位于所述至少一个集成电路元件和所述窗框之间的密封材料。

公开(公告)号：US06933813B2

公开(公告)日：2005-08-23

申请号：US10714376

申请日：2003-11-12

申请人： William Edward Burdick, Jr. ,  James Wilson Rose ,  Kevin Matthew Durocher ,  Raymond Albert Fillion

发明人： William Edward Burdick, Jr. ,  James Wilson Rose ,  Kevin Matthew Durocher ,  Raymond Albert Fillion

IPC分类号： H01L23/52 ,  H01H20060101 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/34 ,  H01L23/50 ,  H01L23/538 ,  H01P1/04 ,  H05K3/06 ,  H05K3/38

CPC分类号： H01L27/14636 ,  H01L24/19 ,  H01L24/82 ,  H01L27/14618 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.

摘要翻译： 互连结构包括：介电层; 所述第一金属化图案包括至少一个具有限定至少一个蚀刻停止开口的周边的蚀刻停止件; 在所述电介质层的一部分上的固化的粘合剂，所述粘合剂不存在于与所述至少一个蚀刻停止件对准的区域中; 并且至少一个电气装置通过所述粘合剂附接到所述电介质层，使得所述至少一个电气装置的有效面积与所述蚀刻停止周界对准。 至少一个电气装置的活动区域还可以与由固化的粘合剂的任选的附加部分限定的至少一个预定区域对准，固化的粘合剂的附加部分粘合地附着到电介质层上，而不粘附到 至少一个电气设备。

公开(公告)号：US06671948B2

公开(公告)日：2004-01-06

申请号：US09681066

申请日：2000-12-18

申请人： William Edward Burdick, Jr. ,  James Wilson Rose ,  Kevin Matthew Durocher ,  Raymond Albert Fillion

发明人： William Edward Burdick, Jr. ,  James Wilson Rose ,  Kevin Matthew Durocher ,  Raymond Albert Fillion

IPC分类号： H05K306

CPC分类号： H01L27/14636 ,  H01L24/19 ,  H01L24/82 ,  H01L27/14618 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

摘要： An interconnection structure includes: a dielectric layer; a first metallization pattern on the dielectric layer, the first metallization pattern including at least one etch stop having a perimeter defining at least one etch stop opening; a cured adhesive on a portion of the dielectric layer, the adhesive not present in an area aligned with the at least one etch stop; and at least one electrical device being attached to the dielectric layer by the adhesive such that an active area of the at least one electrical device is aligned with the etch stop perimeter. The active area of the at least one electrical device may further be aligned with at least one predetermined area defined by an optional additional portion of cured adhesive, the additional portion of the cured adhesive being adhesively attached to the dielectric layer and not adhesively attached to the at least one electrical device.

摘要翻译： 互连结构包括：介电层; 所述第一金属化图案包括至少一个具有限定至少一个蚀刻停止开口的周边的蚀刻停止件; 在所述电介质层的一部分上的固化的粘合剂，所述粘合剂不存在于与所述至少一个蚀刻停止件对准的区域中; 并且至少一个电气装置通过所述粘合剂附接到所述电介质层，使得所述至少一个电气装置的有效面积与所述蚀刻停止周界对准。 至少一个电气装置的活动区域还可以与由固化的粘合剂的任选的附加部分限定的至少一个预定区域对准，固化的粘合剂的附加部分粘合地附着到电介质层上，而不粘附到 至少一个电气设备。

公开(公告)号：US11749909B2

公开(公告)日：2023-09-05

申请号：US18079288

申请日：2022-12-12

申请人： Raymond Albert Fillion

发明人： Raymond Albert Fillion

IPC分类号： G01S15/04 ,  H01Q3/46 ,  H01Q21/22 ,  H01Q15/02 ,  G01S7/03 ,  H01Q3/26 ,  H01Q1/32

CPC分类号： H01Q21/22 ,  G01S7/032 ,  H01Q3/2676 ,  H01Q15/02 ,  H01Q1/3233

摘要： A phased array antenna system comprising a plurality of isotropic radiating elements and/or omnidirectional receiving elements addressing close in fields and a plurality of non-isotropic radiating elements and/or non-omnidirectional receiving elements addressing remote fields with the combined elements used to extend the maximum range of the antenna system without increasing the number of element nor the output power of the antenna. The non-isotropic radiating elements and/or the non-omnidirectional receiving elements can be formed by adding focusing structures such as lenses or reflective structures in the radiating path of isotropic radiating elements and/or omnidirectional receiving elements. Antennas with combined isotropic radiating and non-isotropic radiating elements can be utilized for electromagnetic phased array radar, communication and imaging systems and for acoustic phased array sonar or ultrasound systems.