公开(公告)号：US06703317B1

公开(公告)日：2004-03-09

申请号：US10356248

申请日：2003-01-30

申请人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying-Lung Wang

IPC分类号： H01L21302

CPC分类号： H01L21/3105 ,  H01L21/02052 ,  H01L21/76826 ,  H01L21/76837 ,  Y10S438/906

摘要： A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.

摘要翻译： 一种减少晶片工艺表面上的电荷不平衡的方法，包括提供具有包括最上面的第一材料层的工艺表面的半导体晶片; 根据包括喷射和洗涤中的至少一种的晶片清洁过程清洁工艺表面以在工艺表面产生电荷不平衡; 并且使所述工艺表面进行含氮等离子体处理以至少部分地中和所述电荷不平衡。

公开(公告)号：US06759347B1

公开(公告)日：2004-07-06

申请号：US10401715

申请日：2003-03-27

申请人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying Lung Wang

发明人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Sze-An Wu ,  Ying Lung Wang

IPC分类号： H01L2131

CPC分类号： C23C16/505 ,  C23C16/401 ,  H01L21/31629 ,  H01L21/76819 ,  H01L21/76829

摘要： A method of reducing plasma induced damage in semiconductor devices and fluorine damage to a metal containing layer including providing a semiconductor wafer including semiconductor devices including a gate oxide and a process surface including metal lines; carrying out a first high density plasma chemical vapor deposition (HDP-CVD) process to controllably produce a silicon rich oxide (SRO) layer including a relatively increased thickness at a center portion of the process surface compared to a peripheral portion of the process surface; and, carrying out a second HDP-CVD process in-situ to deposit a fluorine doped silicon dioxide layer over the SRO layer to fill a space between the metal lines.

摘要翻译： 一种降低半导体器件中的等离子体诱发损伤的方法和对含金属层的氟损伤的方法，包括提供包括包括栅极氧化物的半导体器件和包括金属线的工艺表面的半导体晶片的半导体晶片; 执行第一高密度等离子体化学气相沉积（HDP-CVD）工艺，以可控地产生富硅氧化物（SRO）层，其与过程表面的周边部分相比在工艺表面的中心部分包​​括相对增加的厚度; 并且原位进行第二HDP-CVD工艺以在SRO层上沉积氟掺杂的二氧化硅层以填充金属线之间的空间。

公开(公告)号：US06479098B1

公开(公告)日：2002-11-12

申请号：US09747135

申请日：2000-12-26

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1640

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

摘要翻译： 一种用于减少具有室等离子体处理区域部件的处理室10中的污染物的方法，包括以下步骤。 腔室等离子体处理区域部件被清洁。 然后如下调节室。 在室等离子体处理区域部件上形成第一USG层。 在第一USG层上形成FSG层。 在FSG层上形成第二个USG层。 其中USG，FSG和第二USG层包括UFU季电影。 UFU季涂膜处理室的室等离子体处理区域部件包括：室上的内部USG层等离子体处理区域部件; 内部USG层上的FSG层; 以及FSG层上的外部USG层。

公开(公告)号：US06602560B2

公开(公告)日：2003-08-05

申请号：US10196850

申请日：2002-07-16

申请人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Long Wang ,  Pei-Fen Chou

发明人： Yi-Lung Cheng ,  Wen-Kung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Long Wang ,  Pei-Fen Chou

IPC分类号： C23C1640

CPC分类号： C23C16/4405 ,  B08B7/0035

摘要： A method of removing residual fluorine present in a HDP-CVD chamber which includes a high pressure seasoning process, a dry-cleaning process, and a low-pressure deposition process.

摘要翻译： 一种除去存在于HDP-CVD室中的残余氟的方法，其包括高压调味处理，干洗处理和低压沉积工艺。

公开(公告)号：US20050009367A1

公开(公告)日：2005-01-13

申请号：US10615744

申请日：2003-07-09

申请人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Lang Wang ,  Pei-Fen Chou

发明人： Yi-Lung Cheng ,  Ming-Hwa Yoo ,  Szu-An Wu ,  Ying-Lang Wang ,  Pei-Fen Chou

IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/76 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02131 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/76837

摘要： A method of forming an FSG film comprising the following steps. A structure is provided. An FSG film is formed over the structure by an HDP-CVD process under the following conditions: no Argon (Ar)—side sputter; SiF4 flow: from about 53 to 63 sccm; an N2 flow: from about 25 to 35 sccm; and an RF power to provide a uniform plasma density.

摘要翻译： 一种形成FSG膜的方法，包括以下步骤。 提供了一种结构。 在以下条件下通过HDP-CVD工艺在该结构上形成FSG膜：无氩（Ar）侧溅射; SiF4流量：约53至63sccm; N2流量：约25至35sccm; 和RF功率以提供均匀的等离子体密度。

公开(公告)号：US06815072B2

公开(公告)日：2004-11-09

申请号：US10256714

申请日：2002-09-27

申请人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： B05C1100

CPC分类号： H01J37/32477 ,  C23C16/4404 ,  Y10T428/2495 ,  Y10T428/265

摘要： A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

公开(公告)号：US06815007B1

公开(公告)日：2004-11-09

申请号：US10086258

申请日：2002-03-04

申请人： Ming-Hwa Yoo ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

发明人： Ming-Hwa Yoo ,  Shih-Chi Lin ,  Yi-Lung Cheng ,  Szu-An Wu ,  Ying-Lang Wang

IPC分类号： C23C1622

CPC分类号： H01J37/32862 ,  C23C16/308 ,  C23C16/401 ,  C23C16/4404 ,  H01J2237/022

摘要： A method for reducing contaminants in a processing chamber having an inner wall by seasoning the walls. The method comprising the following steps. A first USG film is formed over the processing chamber inner wall. An FSG film is formed over the first USG film. A second USG film is formed over the FSG film. A nitrogen-containing film is formed over the second USG film wherein the first USG film, the FSG film, the second USG film and the nitrogen-containing film comprise a UFUN season film.

公开(公告)号：US20050153537A1

公开(公告)日：2005-07-14

申请号：US10753637

申请日：2004-01-08

申请人： Yi-Lung Cheng ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Ying-Lung Wang

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76826

摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.

摘要翻译： 公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。 将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。 氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。 复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

公开(公告)号：US20050121751A1

公开(公告)日：2005-06-09

申请号：US10729217

申请日：2003-12-04

申请人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

发明人： Shiu-Ko Jangjian ,  Jun Wu ,  Chi-Wen Liu ,  Ying-Lung Wang ,  Yi-Lung Cheng ,  Michael Chang ,  Szu-An Wu

IPC分类号： H01L21/31 ,  H01L21/316 ,  H01L21/76 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L23/5329 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76835 ,  H01L21/7684 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.

公开(公告)号：US07296532B2

公开(公告)日：2007-11-20

申请号：US10323950

申请日：2002-12-18

申请人： Yi-Lung Cheng ,  Mo-Chen Liao ,  Eric Tsai ,  Sze-Au Wu ,  Ying-Lung Wang

发明人： Yi-Lung Cheng ,  Mo-Chen Liao ,  Eric Tsai ,  Sze-Au Wu ,  Ying-Lung Wang

IPC分类号： C23C16/00

CPC分类号： C23C16/45561 ,  C23C16/4412 ,  C23C16/455 ,  C23C16/509

摘要： A method and reactant gas bypass system for carrying out a plasma enhanced chemical vapor deposition (PECVD) process with improved gas flow stability to avoid unionized reactant precursors and thickness non-uniformities the method including providing a semiconductor process wafer having a process surface within a plasma reactor chamber for carrying out at least one plasma process; supplying at least one reactant gas flow at a selected flow rate to bypass the plasma reactor chamber for a period of time to achieve a pre-determined flow rate stability; and, redirecting the at least one reactant gas flow into the plasma reactor chamber to carry out the at least one plasma process.

摘要翻译： 一种用于执行等离子体增强化学气相沉积（PECVD）工艺的方法和反应物气体旁通系统，其具有改进的气体流动稳定性以避免未结合的反应物前体和厚度不均匀性，该方法包括提供具有等离子体内的工艺表面的半导体工艺晶片 反应室，用于进行至少一个等离子体工艺; 以选定的流速供应至少一个反应气体流以绕过等离子体反应器室一段时间以达到预定的流速稳定性; 以及将所述至少一个反应物气流重定向到所述等离子体反应器室中以执行所述至少一个等离子体过程。