公开(公告)号：US20120161336A1

公开(公告)日：2012-06-28

申请号：US13089289

申请日：2011-04-18

申请人： Yu-Min Lin ,  Chau-Jie Zhan ,  Su-Tsai Lu

发明人： Yu-Min Lin ,  Chau-Jie Zhan ,  Su-Tsai Lu

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/345 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/14131 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16507 ,  H01L2224/17505 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81224 ,  H01L2224/81234 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81948 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/32225

摘要： A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

摘要翻译： 提供了一种半导体器件及其组装方法。 半导体器件包括芯片，载体，多个第一导电元件和多个第二导电元件。 芯片具有多个第一焊盘。 载体具有多个第二垫。 第二垫对应于第一垫。 每个第一导电元件设置在第一焊盘之一和第二焊盘中的一个之间。 每个第二导电元件设置在第一焊盘之一和第二焊盘中的一个之间。 第二导电元件的金属间化合物的体积比大于第一导电元件的金属间化合物的体积比。

公开(公告)号：US08415795B2

公开(公告)日：2013-04-09

申请号：US13089289

申请日：2011-04-18

申请人： Yu-Min Lin ,  Chau-Jie Zhan ,  Su-Tsai Lu

发明人： Yu-Min Lin ,  Chau-Jie Zhan ,  Su-Tsai Lu

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/17 ,  H01L21/563 ,  H01L23/345 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/14131 ,  H01L2224/14505 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16507 ,  H01L2224/17505 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81224 ,  H01L2224/81234 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81948 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/32225

摘要： A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

摘要翻译： 提供了一种半导体器件及其组装方法。 半导体器件包括芯片，载体，多个第一导电元件和多个第二导电元件。 芯片具有多个第一焊盘。 载体具有多个第二垫。 第二垫对应于第一垫。 每个第一导电元件设置在第一焊盘之一和第二焊盘中的一个之间。 每个第二导电元件设置在第一焊盘之一和第二焊盘中的一个之间。 第二导电元件的金属间化合物的体积比大于第一导电元件的金属间化合物的体积比。

公开(公告)号：US08598686B2

公开(公告)日：2013-12-03

申请号：US12891734

申请日：2010-09-27

申请人： Tao-Chih Chang ,  Su-Tsai Lu ,  Jing-Yao Chang ,  Chau-Jie Zhan

发明人： Tao-Chih Chang ,  Su-Tsai Lu ,  Jing-Yao Chang ,  Chau-Jie Zhan

IPC分类号： H01L23/544

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2224/81

摘要： The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench.

摘要翻译： 本发明提供一种电子器件封装结构及其制造方法。 电子器件封装结构包括具有有源表面和底表面的芯片。 电介质层设置在芯片的有源表面上。 通过介电层形成至少一个沟槽。 第一保护层覆盖电介质层和沟槽的侧壁。 第二保护层覆盖第一保护层，填充沟槽。

公开(公告)号：US20100207266A1

公开(公告)日：2010-08-19

申请号：US12426967

申请日：2009-04-21

申请人： Tao-Chih Chang ,  Su-Tsai Lu ,  Chau-Jie Zhan ,  Chun-Chih Chuang ,  Jing-Ye Juang

发明人： Tao-Chih Chang ,  Su-Tsai Lu ,  Chau-Jie Zhan ,  Chun-Chih Chuang ,  Jing-Ye Juang

IPC分类号： H01L23/52

CPC分类号： H01L23/49811 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13011 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/83141 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05005 ,  H01L2224/05541

摘要： A chip package structure including a substrate, a plurality of electrodes, a chip, and a plurality of bumps is provided. Each of the electrodes has a bottom portion and an annular element, wherein the bottom portion is disposed on the substrate, the annular element is disposed on the bottom portion, and the bottom portion and the annular element define a containing recess. The chip is disposed above the substrate and has an active surface facing the substrate and a plurality of pads disposed on the active surface. The bumps are respectively disposed on the pads and respectively inserted into the containing recesses. The melting point of the electrodes is higher than that of the bumps. A chip package method is also provided.

摘要翻译： 提供了包括基板，多个电极，芯片和多个凸块的芯片封装结构。 每个电极具有底部和环形元件，其中底部设置在基板上，环形元件设置在底部上，底部和环形元件限定容纳凹部。 芯片设置在基板上方并且具有面向基板的有源表面和设置在有源表面上的多个焊盘。 凸块分别设置在焊盘上并分别插入容纳凹部中。 电极的熔点高于凸块的熔点。 还提供了芯片封装方法。

公开(公告)号：US20110227190A1

公开(公告)日：2011-09-22

申请号：US12891734

申请日：2010-09-27

申请人： Tao-Chih Chang ,  Su-Tsai Lu ,  Jing-Yao Chang ,  Chau-Jie Zhan

发明人： Tao-Chih Chang ,  Su-Tsai Lu ,  Jing-Yao Chang ,  Chau-Jie Zhan

IPC分类号： H01L23/58

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2224/81

摘要： The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench.

摘要翻译： 本发明提供一种电子器件封装结构及其制造方法。 电子器件封装结构包括具有有源表面和底表面的芯片。 电介质层设置在芯片的有源表面上。 通过介电层形成至少一个沟槽。 第一保护层覆盖电介质层和沟槽的侧壁。 第二保护层覆盖第一保护层，填充沟槽。

公开(公告)号：US20120168933A1

公开(公告)日：2012-07-05

申请号：US12981475

申请日：2010-12-30

申请人： Su-Tsai Lu ,  Jing-Ye Juang ,  Yu-Min Lin

发明人： Su-Tsai Lu ,  Jing-Ye Juang ,  Yu-Min Lin

IPC分类号： H01L23/485 ,  H01L23/498

CPC分类号： H01L23/295 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29386 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A wafer level molding structure and a manufacturing method thereof are provided. A molding structure includes a first chip and a second chip and an adhesive layer there between. The first chip includes a first back side, a first front side and a plurality of lateral sides, in which a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through-hole vias is disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials covering the lateral sides of the first chip, and electrically connect the second back side bumps with the first front side bumps. The adhesive materials include a plurality of conductive particles and/or a plurality of non-conductive particles.

摘要翻译： 提供了晶片级成型结构及其制造方法。 模制结构包括第一芯片和第二芯片以及其间的粘合剂层。 第一芯片包括第一前侧，第一前侧和多个侧边，多个第一前侧凸块设置在第一前侧。 第二芯片包括第二后侧和第二前侧，并且多个第二后侧凸块和第二前侧凸块分别设置在第二后侧和第二前侧上。 多个通孔通孔设置在第二芯片中，并且将第二背面凸块电连接到第二前侧凸块。 粘合剂材料覆盖第一芯片的侧面，并且将第二背面凸块与第一前侧凸块电连接。 粘合剂材料包括多个导电颗粒和/或多个非导电颗粒。

公开(公告)号：US08384215B2

公开(公告)日：2013-02-26

申请号：US12981475

申请日：2010-12-30

申请人： Su-Tsai Lu ,  Jing-Ye Juang ,  Yu-Min Lin

发明人： Su-Tsai Lu ,  Jing-Ye Juang ,  Yu-Min Lin

IPC分类号： H01L23/485 ,  H01L23/496

CPC分类号： H01L23/295 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29386 ,  H01L2224/73104 ,  H01L2224/73153 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

摘要： A wafer level molding structure including a first chip, a second chip and an adhesive layer therebetween is provided. The first chip includes a first back side, a first front side and a plurality of lateral sides, and a plurality of first front side bumps are disposed on the first front side. The second chip includes a second back side and a second front side, and a plurality of second back side bumps and second front side bumps are respectively disposed on the second back side and the second front side. A plurality of through electrodes are disposed in the second chip, and electrically connected the second back side bumps to the second front side bumps. Adhesive materials including a plurality of conductive particles cover the lateral sides, and electrically connect the second back side bumps with the first front side bumps.

摘要翻译： 提供了包括第一芯片，第二芯片和其间的粘合剂层的晶片级模制结构。 第一芯片包括第一背面，第一前侧和多个侧面，并且多个第一前侧凸块设置在第一前侧。 第二芯片包括第二后侧和第二前侧，并且多个第二后侧凸块和第二前侧凸块分别设置在第二后侧和第二前侧上。 多个贯通电极设置在第二芯片中，并且将第二背面凸块电连接到第二前侧凸块。 包括多个导电颗粒的粘合材料覆盖侧面，并且将第二后侧凸起与第一前侧凸起电连接。

公开(公告)号：US08134230B2

公开(公告)日：2012-03-13

申请号：US12508575

申请日：2009-07-24

申请人： Tsung-Fu Yang ,  Su-Tsai Lu

发明人： Tsung-Fu Yang ,  Su-Tsai Lu

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00

摘要： A sealed joint structure of device includes a buffer bump layer, conductive joint portions and a sealed joint portion. The buffer bump layer disposed between a device and a substrate includes first parts and a second part surrounding the first parts. Each of the conductive joint portions includes a first electrode covering each of the first parts and a second electrode on the substrate, and each of the first electrodes is electrically connected to the second electrode. The sealed joint portion includes a joint ring located on the substrate and is jointed with the second part to form a hermetic space between the device and the substrate.

摘要翻译： 密封的器件结构结构包括缓冲凸起层，导电接合部分和密封接合部分。 设置在装置和基板之间的缓冲凸块层包括第一部分和围绕第一部分的第二部分。 每个导电接合部分包括覆盖基板上的每个第一部分的第一电极和第二电极，并且每个第一电极电连接到第二电极。 密封接头部分包括位于基板上并与第二部分接合的接合环，以在设备和基板之间形成密封空间。

公开(公告)号：US20090224362A1

公开(公告)日：2009-09-10

申请号：US12205935

申请日：2008-09-08

申请人： Su-Tsai Lu ,  Wen-Hwa Chen ,  Hsien-Chie Cheng ,  Yun-Chiao Chen

发明人： Su-Tsai Lu ,  Wen-Hwa Chen ,  Hsien-Chie Cheng ,  Yun-Chiao Chen

IPC分类号： H01L27/06 ,  H01L21/20

CPC分类号： H01L28/86 ,  H01L28/82 ,  H01L28/90

摘要： After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.

摘要翻译： 在旨在使半导体器件小型化的制造工艺之后，随机存取存储器（RAM）中的堆叠电容器的表面积显着减小，并且其容量因此降低，这又导致电容器不能正常工作。 本发明提供了一种由外部环形管和具有凹凸表面的中心柱构成的复合下电极结构，以增加有限存储单元内的电容器的表面积，从而提高容量。 为了加强电容器的结构的强度，外部环形管具有沿着短轴方向的椭圆形的径向横截面和较厚的厚度。

公开(公告)号：US20080081395A1

公开(公告)日：2008-04-03

申请号：US11984014

申请日：2007-11-13

申请人： Yuan-Chang Huang ,  Tai-Hung Chen ,  Yao-Sheng Lin ,  Su-Tsai Lu

发明人： Yuan-Chang Huang ,  Tai-Hung Chen ,  Yao-Sheng Lin ,  Su-Tsai Lu

IPC分类号： H01L31/18

CPC分类号： H01L27/14683 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.